Patents by Inventor KyeHyung Lee

KyeHyung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10333506
    Abstract: Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Lorenzo Crespi, Kyehyung Lee, Davide Cartasegna
  • Publication number: 20180316349
    Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Yongjie CHENG, Lei ZHU, Kyehyung LEE
  • Publication number: 20180131359
    Abstract: Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.
    Type: Application
    Filed: November 8, 2017
    Publication date: May 10, 2018
    Inventors: Lorenzo Crespi, Kyehyung Lee, Davide Cartasegna
  • Patent number: 9276525
    Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 1, 2016
    Assignee: CONEXANT SYSTEMS, INC.
    Inventors: Brian W. Friend, Lorenzo Crespi, Kyehyung Lee
  • Patent number: 9024603
    Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: May 5, 2015
    Assignee: Conexant Systems, Inc.
    Inventors: Brian W. Friend, Kyehyung Lee
  • Publication number: 20140247091
    Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 4, 2014
    Applicant: Conexant Systems, Inc.
    Inventors: Brian W. Friend, Lorenzo Crespi, Kyehyung Lee
  • Publication number: 20130200872
    Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.
    Type: Application
    Filed: January 31, 2013
    Publication date: August 8, 2013
    Inventors: Brian W. Friend, Kyehyung Lee
  • Patent number: 7952508
    Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 31, 2011
    Assignee: Conexant Systems, Inc.
    Inventors: Lorenzo Crespi, Ketan B Patel, Kyehyung Lee
  • Publication number: 20110050467
    Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.
    Type: Application
    Filed: September 2, 2009
    Publication date: March 3, 2011
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Lorenzo Crespi, Ketan B. Patel, Kyehyung Lee
  • Patent number: 7348821
    Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Jianping Xu, KyeHyung Lee, Fabrice Paillet, David Rennie, Tanay Karnik
  • Publication number: 20060061399
    Abstract: A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.
    Type: Application
    Filed: September 22, 2004
    Publication date: March 23, 2006
    Inventors: Jianping Xu, KyeHyung Lee, Fabrice Paillet, David Rennie, Tanay Karnik
  • Patent number: 6958640
    Abstract: An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: October 25, 2005
    Assignee: Intel Corporation
    Inventors: KyeHyung Lee, Jianping Xu, Fabrice Paillet, Tanay Karnik
  • Publication number: 20050140412
    Abstract: An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventors: KyeHyung Lee, Jianping Xu, Fabrice Paillet, Tanay Karnik