Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Abstract: An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.

Abstract: An apparatus in a PWM modulator includes a triangular wave generator that generates a triangular wave and a comparator that is responsive to a signal input to generate a signal output. An output of the PWM modulator is responsive to the comparator signal output. A polarity inversion circuit, coupled between the triangular wave generator and the comparator, is configured in one of the following ways: to provide the triangular wave to the comparator when the triangular wave has a first slope polarity and to provide a polarity-inverted version of the triangular wave to the comparator when the triangular wave has a second slope polarity opposite the first slope polarity; and to provide the signal input to the comparator when the triangular wave has the first slope polarity and to provide a polarity-inverted version of the signal input to the comparator when the triangular wave has the second slope polarity.

Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Abstract: Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

Abstract: Systems and methods according to one or more embodiments are provided for a current comparator with biasing circuitry to provide for low power consumption and high-speed performance. In one example, a system includes an input port to receive a current pulse and an amplifier configured to provide a voltage pulse at an output port in response to the current pulse. The system also includes a first biasing circuit coupled between the output port and the input port to selectively limit a voltage at the input port. The system further includes a second biasing circuit coupled to the amplifier to selectively adjust a bias of the amplifier.

Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.

Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Abstract: A circuit comprising a peak detector configured to receive a positive voltage input, a negative voltage input and a reference current source input and to output a peak signal data value. A fast attack current source control coupled to the peak detector and configured to generate a current source control signal as a function of the peak signal data value. A slow decay control coupled to the fast attack current source control and configured to reduce the current source control signal based on a predetermined or user-selected decay rate. A variable current source coupled to the fast attack current source control and configured to generate a variable current as a function of the current source control signal. Amplifier circuitry coupled to the variable current source, the amplifier circuitry configured to receive the variable current.

Abstract: A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.

Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.