Patents by Inventor Kyengmun KANG

Kyengmun KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956967
    Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunggil Kim, Kyengmun Kang, Hyeeun Hong
  • Patent number: 11764268
    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, par
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: September 19, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunggil Kim, Kyengmun Kang, Juyon Suh, Hyeeun Hong
  • Publication number: 20220278201
    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, par
    Type: Application
    Filed: May 20, 2022
    Publication date: September 1, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sunggil KIM, Kyengmun KANG, Juyon SUH, Hyeeun HONG
  • Patent number: 11342415
    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, par
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 24, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunggil Kim, Kyengmun Kang, Juyon Suh, Hyeeun Hong
  • Publication number: 20210408028
    Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.
    Type: Application
    Filed: April 5, 2021
    Publication date: December 30, 2021
    Inventors: SUNGGIL KIM, KYENGMUN KANG, HYEEUN HONG
  • Publication number: 20210313427
    Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, par
    Type: Application
    Filed: October 30, 2020
    Publication date: October 7, 2021
    Inventors: Sunggil KIM, Kyengmun KANG, Juyon SUH, Hyeeun HONG