Patents by Inventor KYEO RAE LEE

KYEO RAE LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10579564
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hee Yoo, Jae Geun Yun, Bub Chul Jeong, Dong Soo Kang, Kyeo Rae Lee, Seong Min Jo
  • Publication number: 20190171597
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Application
    Filed: February 12, 2019
    Publication date: June 6, 2019
    Inventors: JUN HEE YOO, JAE GEUN YUN, BUB CHUL JEONG, DONG SOO KANG, KYEO RAE LEE, SEONG MIN JO
  • Patent number: 10229079
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hee Yoo, Jae Geun Yun, Bub Chul Jeong, Dong Soo Kang, Kyeo Rae Lee, Seong Min Jo
  • Publication number: 20180276160
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: JUN HEE YOO, Jae Geun Yun, Bub Chul Jeong, Dong Soo Kang, Kyeo Rae Lee, Seong Min Jo
  • Patent number: 9984019
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hee Yoo, Jae Geun Yun, Bub Chul Jeong, Dong Soo Kang, Kyeo Rae Lee, Seong Min Jo
  • Publication number: 20160196227
    Abstract: A system on chip (SoC) is present that includes a plurality of master interfaces, a plurality of slave interfaces, and an interface circuit which is connected between the plurality of master interfaces and the plurality of slave interfaces and includes a plurality of components. When a first master interface among the plurality of master interfaces and a first slave interface among the plurality of slave interfaces are paired, a first group of the components which forms a first signal path between the first master interface and the first slave interface among the plurality of components is enabled according to a control of the first master interface.
    Type: Application
    Filed: December 8, 2015
    Publication date: July 7, 2016
    Inventors: JUN HEE YOO, JAE GEUN YUN, BUB CHUL JEONG, DONG SOO KANG, KYEO RAE LEE, SEONG MIN JO