Abstract: A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions.

Abstract: A method of forming an alignment layer with a multi-domain is provided. The alignment layer is formed on a substrate. A mask having a transmission part and a shielding part is aligned over the substrate. First and second alignment directions in the alignment layer are formed by irradiating an ion beam onto the substrate at different irradiation angles. Using the aforementioned ion-beam irradiation process eliminates the need for multiple rubbing processes to create the multi-domain alignment layer.

Abstract: A method of forming an alignment layer with a multi-domain is provided. The alignment layer is formed on a substrate. A mask having a transmission part and a shielding part is aligned over the substrate. First and second alignment directions in the alignment layer are formed by irradiating an ion beam onto the substrate at different irradiation angles. Using the aforementioned ion-beam irradiation process eliminates the need for multiple rubbing processes to create the multi-domain alignment layer.

Abstract: A parallel test circuit for a semiconductor memory device includes a divided output driver configuration capable of generating a tri-state output. The parallel test circuit has a main output driver for outputting a signal having a first level when cell arrays are stored with data having the same level, and a sub output driver for outputting a signal having an intermediate level when the cell arrays are stored with data having different levels. Because the parallel test circuit can accurately detect errors, it can perform a reliable parallel test for pass/fail devices, and can be used to check device characteristics or for a speed sort test.

Abstract: A semiconductor memory device having a parallel test mode for simultaneously testing a plurality of memory cells, comprising: a memory cell array having N numbers of memory cell blocks, wherein each memory cell block includes the plurality of memory cells and outputs first and second complementary data signals, the N being a positive integer; M numbers of first logical operation circuits responsive to a parallel test mode enable signal, each first logical operation circuit for carrying out a logical operation with respect to first and second complementary data signals outputted from at least two memory cell blocks, thereby generating first and second logical operation signals, wherein the N is greater than the M; a second logical operation circuit for carrying out the logical operation with respect to the first and second logical operation signals, thereby generating third and fourth logical operation signals; a pair of global data bus lines coupled between each of first logical operation circuit and said sec