Abstract: A method for generating a parity check matrix of a block LDPC code. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity.

Abstract: A signal transmission apparatus in a communication system is disclosed. A channel interleaver generates an interleaved vector by channel-interleaving a Low Density Parity Check (LDPC) codeword according to a channel interleaving rule, and a modulator generates a modulation symbol by modulating the interleaved vector according to a modulation scheme. The channel interleaving rule is one of a first channel interleaving rule and a second channel interleaving rule. The first channel interleaving rule is a rule for setting degree distribution for nodes in a factor graph of the LDPC codeword separately for individual levels supported by the modulation scheme. The second channel interleaving rule is a rule for allowing coded bits included in the LDPC codeword to be interleaved according to an unequal error characteristic of the modulation scheme.

Abstract: Disclosed is an apparatus and a method for transmitting/receiving a signal in a communication system, which generates an Affine Permutation Matrix-Low Density Parity Check (APM-LDPC) codeword by encoding an information vector in an APM-LDPC encoding scheme which is a preset structured LDPC encoding scheme, and detects the information vector by decoding the signal in a decoding scheme corresponding to the APM-LDPC encoding scheme, thereby making it possible to generate a Low Density Parity Check (LDPC) code in the form of maximizing a girth while minimizing complexity.

Abstract: Provided are an apparatus and method for transmtting/receiving signal, supporting a variable coding rate, in a communication system. The method includes receiving an information vector, generating a child parity check matrix based on a parent parity check matrix according to a coding rate to be applied for generating a block Low Density Parity Check (LDPC) codeword using the information vector, and encoding the information vector into the block LDPC codeword according to the child parity check matrix.

Abstract: Disclosed is a method for transmitting a channel signal in a base station of a mobile communication system which scrambles a common channel signal using a primary scrambling code for identifying the base station. The method comprises determining an identifier (ID) of a secondary scrambling code, upon receipt of a dedicated channel assignment request from a mobile station; transmitting the determined ID of the secondary scrambling code to the mobile station and awaiting a response; upon receipt of a response message from the mobile station, generating a primary scrambling code and a secondary scrambling code using an ID of the primary scrambling code and said ID of the secondary scrambling code; and scrambling a common channel signal using the primary scrambling code, scrambling a dedicated channel signal using the secondary scrambling code, and transmitting the scrambled channel signals.

Abstract: Disclosed is a method and apparatus for completely recovering received data with high reliability using LDPC codes without short-sized cycles in a digital communication system using an error-correcting code. The method includes performing exponent conversion of a predetermined number of exponent matrixes stored in advance in a memory so as to generate new exponent matrixes based on the exponent conversion, and generating new LDPC codes using the new exponent matrixes.

Abstract: Disclosed is an apparatus for encoding TFCI bits in an asynchronous CDMA mobile communication system including a UE and a Node B for transmitting packet data to the UE. A TFCI bit generator creates the TFCI bits, the number of which is variable depending on an information bit ratio of the first channel to the second channel. A code length information generator generates code length information for setting a length of a codeword according to the information bit ratio. A Walsh code generator generates first to fifth basis Walsh codewords. A sequence generator generates an all-1 sequence. A mask generator generates first to fourth basis masks. First to tenth multipliers multiply the TFCI bits by the first to fifth basis Walsh codewords, the all-1 sequence and the first to fourth basis masks, respectively. An adder adds outputs of the first to tenth multipliers. A puncturer punctures a codeword output from the adder according to the code length information.

Abstract: Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

Abstract: An apparatus and method for coding a block Low Density Parity Check (LDPC) code having a variable coding rate. The apparatus receives an information word and encodes the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix, depending on a coding rate to be applied when generating the information word into the block LDPC code.

Abstract: An apparatus and method for coding a semi-systematic block low density parity check (LDPC) code in which an information word is received and coded into a codeword including the information word, a first parity, a second parity, and a third parity, based on one of a first parity check matrix and a second parity check matrix, depending on a size to be applied when generating the information word into a semi-systematic block LDPC code. A part having a degree being at least equal to a predetermined degree is punctured from the information word, generating the semi-systematic block LDPC code. The semi-systematic block LDPC code includes the information word, the part of which was punctured, the first parity, the second parity, and the third parity.

Abstract: Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code based on one of a first parity check matrix and a second parity check matrix depending on a length to be applied when generating the information word into the block LDPC code.

Abstract: Disclosed is a method for transmitting a channel signal in a base station of a mobile communication system which scrambles a common channel signal using a primary scrambling code for identifying the base station. The method comprises determining an identifier (ID) of a secondary scrambling code, upon receipt of a dedicated channel assignment request from a mobile station; transmitting the determined ID of the secondary scrambling code to the mobile station and awaiting a response; upon receipt of a response message from the mobile station, generating a primary scrambling code and a secondary scrambling code using an ID of the primary scrambling code and said ID of the secondary scrambling code; and scrambling a common channel signal using the primary scrambling code, scrambling a dedicated channel signal using the secondary scrambling code, and transmitting the scrambled channel signals.

Abstract: A method for generating a parity check matrix of a block LDPC code is disclosed. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity.

Abstract: A device for generating a quasi-orthogonal code mask in a communication system. A counter generates first to eighth counter signals x1-x8 representing Bent functions. A logic operator receives the first to eighth counter signals x1-x8 and performs an operation, for example x1*x2+x1*x3+x1*x4+x1*x5+x1*x7+x1*x8+x2*x6+x2*x7+x3*x4+x3*x5+x3*x6+x4*x5+x4*x6+x4*x7+x4*x8+3x5*x7+x7*x8+x1+x2+x5+x7, to generate a mask signal.

Abstract: A device and method for generating a binary quasi-orthogonal code in a CDMA communication system. The method comprises generating an m-sequence, and specific left and right sequences having a good full correlation property with the m-sequence; column permuting the specific left and right sequences in a column permutation method used when converting the m-sequence to a Walsh orthogonal code, and connecting the left sequences to the right sequences to generate mask candidates; operating the mask candidates and Walsh orthogonal codes having the same length as the mask candidates to generate quasi-orthogonal code candidate families; and selecting a quasi-orthogonal code out of the generated quasi-orthogonal code candidate families, the selected quasi-orthogonal code satisfying a partial correlation property with the Walsh orthogonal codes, and selecting a mask related to generation of the selected quasi-orthogonal code.

Abstract: A method for generating a quaternary complex quasi-orthogonal code in a CDMA communication system is disclosed. The method comprises generating an M-sequence and then generating specific sequences having a good full correlation property with the M-sequence; generating a column permutation function for converting the M-sequence to a Walsh code; generating candidate masks by column shifting the specific sequences with the column permutation function; generating quasi-orthogonal code representatives by operating the candidate masks and the Walsh codes having the same length as that of the candidate masks; and selecting a quasi-orthogonal code satisfying a partial correlation with the Walsh codes, out of the generated quasi-orthogonal code representatives, and selecting a mask related to generation of the selected quasi-orthogonal code.

Abstract: A communication device for a direct sequence code division multiple access (DS-CDMA) communication system is disclosed. The communication device comprises a CRC (Cyclic Redundancy Code) generator for generating CRC bits according to input data bits and adding the generated CRC bits to the input data bits; a channel encoder for encoding the CRC-added data bits using a coding rate R=1/6 convolutional code of a generator polynomial of (457, 755, 551, 637, 625, 727); and an interleaver for interleaving the coded data bits.

Abstract: A method for generating a complex quasi-orthogonal code for channel spreading in a CDMA communication system is disclosed.

Abstract: A channel decoding device for a receiver which receives symbols coded by inserting at least one specific bit in a data frame at a predetermined position. In the channel decoding device, a symbol inserter receives the symbols, inserts a symbol having a specific value at a predetermined specific bit insert position and outputs the received symbols at other positions. A decoder decodes symbols output from the symbol inserter.

Abstract: A device and method for performing channel encoding using a frame structure having a termination effect in a recursive systemic encoder for a communication system. The channel encoding device having: an inserter for inserting at least one predefined bit in an input data bit stream at a predetermined position; and a channel encoder for encoding the bit-inserted data bit stream.