Abstract: A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.

Abstract: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier layer, etching the second ILD layer and the diffusion barrier layer to form a trench, forming a conductive layer to fill the trench, and planarizing the conductive layer to form a metal interconnection electrically connected to the contact plug

Abstract: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier layer, etching the second ILD layer and the diffusion barrier layer to form a trench, forming a conductive layer to fill the trench, and planarizing the conductive layer to form a metal interconnection electrically connected to the contact plug.

Abstract: A method for forming a metal interconnection in an image sensor includes forming a first interlayer dielectric (ILD) layer having a contact plug over a substrate, forming a diffusion barrier layer over the first ILD layer, performing a forming gas annealing, forming a second ILD layer over the diffusion barrier layer, etching the second ILD layer and the diffusion barrier layer to form a trench, forming a conductive layer to fill the trench, and planarizing the conductive layer to form a metal interconnection electrically connected to the contact plug.

Abstract: Provided is a method of forming a metal line in a semiconductor device. According to the present invention, a barrier metal layer, a Zr film, and a Cu thin film is sequentially formed in insides of a dual damascene pattern comprising via holes and trenches. Then, a Zr film is formed on the Cu thin film, and Zr is allowed to be diffused into crystal particles of Cu and interfaces between the crystal particles by carrying out a heat treatment process thereto, so that uniform Cu (Zr) bonds are formed regardless of a depth. As a result, an EM resistance characteristic of the Cu thin film even in narrower and deeper via holes can be improved, and thus reliability of process and an electrical characteristic of a device can be also improved.

Abstract: The present invention relates to a method for forming a high resistive region in a semiconductor device. A pattern having the bottom wider in width than the top such as a trench is formed in a region where an inductor will be formed by means of a two-step or multi-step etch processes. While forming an air gap at the corner of the bottom of the trench using a coverage characteristic of an insulating material, the trench is buried with the insulating material to easily form a high resistive region. Therefore, the present invention can minimize reduction in the quality factor (Q reduction) by preventing, by maximum, the eddy current from being generated in the substrate due to the inductor.

Abstract: The present invention relates to a method of forming a copper metal line in a semiconductor device. A via plug and a copper metal line are independently formed using a single damascene process. A buffer film is formed between the via plug and the copper metal line. It is thus possible to prevent lowering in the yield of a via hole that occurs due to a thermal stress in a subsequent process and diffusion of Cu atoms. Therefore, the yield of the copper metal line can be improved.

Abstract: The present invention provides a method for forming a metal line of a semiconductor device comprising the steps of: forming a via plug on a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate, on which the via plug is formed; forming a trench by patterning the interlayer insulating film in order to form an upper line to be connected to the via plug; depositing a spacer insulating film, which is more invulnerable to a mechanical stress than the interlayer insulating film, on the semiconductor substrate on which the trench is formed; forming a spacer on a side wall of the trench by performing an anisotropic-dry-etching of the spacer insulating film; and forming a metal line by burying the trench with a conductive material.

Abstract: The present invention relates to a method of forming a copper metal line in a semiconductor device. A via plug and a copper metal line are independently formed using a single damascene process. A buffer film is formed between the via plug and the copper metal line. It is thus possible to prevent lowering in the yield of a via hole that occurs due to a thermal stress in a subsequent process and diffusion of Cu atoms. Therefore, the yield of the copper metal line can be improved.

Abstract: A metal interconnection structure of a semiconductor device includes a metal layer having a high surface reflectivity and an ARC layer formed on the metal layer. Here, the ARC layer has a first layer formed on the metal layer and a second layer formed on the first layer. The first layer has a good step coverage property, while the second layer has a low surface reflectivity. Preferably, the first layer is a polysilicon layer, while the second layer is a CVD-TiN layer. The polysilicon layer is formed to the thickness of 50 to 300 Å, while the CVD-TiN layer is formed to the thickness of 100 to 300 Å. Furthermore, the metal layer is made of one material selected from the group consisting of aluminum, aluminum alloy, tungsten, and copper. Preferably, the metal layer is an aluminum layer.

Abstract: A method for fabricating a capacitor of a semiconductor device which stabilizes the operation of electrodes of the capacitor and improves the operational characteristic and reliability of the semiconductor device.

Abstract: A method for fabricating a capacitor of a semiconductor device which stabilizes the operation of electrodes of the capacitor and improves the operational characteristic and reliability of the semiconductor device.

Abstract: The present invention discloses a method of forming a plug in a semiconductor device. Metals having different properties are employed to induce the growth of the metals in fixed direction within the contact hole so as to prevent an over-etching which is generated due to a difference of density depending on the growth direction of the metal in the contact hole. Upon a full-surface etching process for forming a plug, the step difference generating on top of the contact hole can be minimized, thereby improving the step coverage of the metal during a subsequent metalization process and increasing the electrical characteristic and reliability of the device.

Abstract: A method for fabricating a semiconductor device having a capacitor exhibiting improved insulating and ferroelectric characteristics. The method involves forming a lower insulating layer over a semiconductor substrate, selectively removing the lower insulating layer to form a contact hole, forming a ruthenium film over the lower insulating layer, selectively removing the ruthenium film, thereby forming a lower electrode, and forming a ruthenium oxide film over the lower electrode. A method for forming a metal wiring is also provided.

Abstract: A capacitor structure suitable for the high integration of a semiconductor device is fabricated with a method comprising the steps of: providing a semiconductor substrate; forming a ruthenium-platinum film on the semiconductor substrate; thermally treating the ruthenium-platinum film to grow a ruthenium-platinum oxide on the ruthenium-platinum film; and forming a dielectric film and a conductive layer on the ruthenium-platinum oxide, in sequence.

Abstract: A method for fabricating a capacitor of a semiconductor device which stabilizes the operation of electrodes of the capacitor and improves the operational characteristic and reliability of the semiconductor device.

Abstract: A method for forming a plug in a semiconductor device comprising the steps of: providing openings which expose an underlying layer through an insulating layer; filling selective metal layers into openings such that one of the selective metal layers is overgrown over the surface of the insulating layer in the opening having a lower topology; forming a photoresist layer on the resulting structure; patterning the photoresist layer to expose the upper surface of the overgrown selective metal layer; removing the upper portion of the overgrown selective metal layer, such that the topology of the overgrown selective metal layers is the same as that of the non-overgrown selective metal layer; and forming a metal wiring connected to the selective metal layers.

Abstract: A method of forming a metal interconnection layer of a semiconductor device is disclosed as forming a barrier metal for preventing an atomic migration between a metal film for an interconnection and a lower conduction layer being contacted with the metal film by an ion implantation, so that it prevents metal atoms diffusing into a Si substrate in a deep and narrow contact hole and it makes a copper film to be deposited on an oxide with ease, thereby carrying out an excellent metallization process.