Patents by Inventor Kyeong Min CHAE

Kyeong Min CHAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761763
    Abstract: A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: KangYoul Lee, Kyeong Min Chae
  • Publication number: 20200057574
    Abstract: A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.
    Type: Application
    Filed: April 10, 2019
    Publication date: February 20, 2020
    Inventors: KangYoul LEE, Kyeong Min CHAE
  • Patent number: 10347305
    Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventor: Kyeong Min Chae
  • Patent number: 10191665
    Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: January 29, 2019
    Assignee: SK Hynix Inc.
    Inventor: Kyeong Min Chae
  • Publication number: 20180336936
    Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.
    Type: Application
    Filed: December 21, 2017
    Publication date: November 22, 2018
    Inventor: Kyeong Min CHAE
  • Publication number: 20180004429
    Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.
    Type: Application
    Filed: December 30, 2016
    Publication date: January 4, 2018
    Inventor: Kyeong Min CHAE
  • Patent number: 9607706
    Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 28, 2017
    Assignee: SK Hynix Inc.
    Inventors: Kyeong Min Chae, Min Su Kim
  • Patent number: 9552857
    Abstract: An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response to an internal clock signal; a second address control clock generation unit suitable for generating a second address control clock signal in response to one of an address initialization signal and the first address control clock signal; an address counting unit suitable for counting the second address control clock signal and generating a counting address; and a repair control unit suitable for latching the counting address in response to the second address control clock signal, comparing the latched counting address with a repair address, and generating a redundancy address based on the comparison result.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Kyeong-Min Chae
  • Publication number: 20160111136
    Abstract: An address decoding circuit may include a main address processing block configured to latch a main address, and output a latched main address. The address decoding circuit may include a repair block configured to determine whether the main address corresponds to a failed region, and output a repair address and a repair signal according to a determination result. The address decoding circuit may include a synchronization block configured to synchronize the latched main address, the repair address and the repair signal with a synchronization signal, and output a synchronized main address, a synchronized repair address and a synchronized repair signal. The address decoding circuit may include a decoder configured to decode any one of the synchronized main address and the synchronized repair address in response to a decoding signal.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 21, 2016
    Inventor: Kyeong Min CHAE