Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

Abstract: A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.

Abstract: A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.

Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.

Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.

Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.

Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.

Abstract: A semiconductor memory device includes a first memory bank and a second memory bank; an address counter unit including: a first address counter suitable for outputting a first counting address signal corresponding to the first memory bank; and a second address counter suitable for outputting a second counting address signal corresponding to the second memory bank; a first output control unit suitable for generating first column address signals in response to the first counting address signal during a data input operation, and generating the first column address signals in response to the second counting address signal during a data output operation; and a second output control unit generating second column address signals in response to the second counting address signal during the data input operation and the data output operation.

Abstract: An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response to an internal clock signal; a second address control clock generation unit suitable for generating a second address control clock signal in response to one of an address initialization signal and the first address control clock signal; an address counting unit suitable for counting the second address control clock signal and generating a counting address; and a repair control unit suitable for latching the counting address in response to the second address control clock signal, comparing the latched counting address with a repair address, and generating a redundancy address based on the comparison result.

Abstract: An address decoding circuit may include a main address processing block configured to latch a main address, and output a latched main address. The address decoding circuit may include a repair block configured to determine whether the main address corresponds to a failed region, and output a repair address and a repair signal according to a determination result. The address decoding circuit may include a synchronization block configured to synchronize the latched main address, the repair address and the repair signal with a synchronization signal, and output a synchronized main address, a synchronized repair address and a synchronized repair signal. The address decoding circuit may include a decoder configured to decode any one of the synchronized main address and the synchronized repair address in response to a decoding signal.