Abstract: A liquid crystal display can include a gate wire including a gate line, a gate pad and a gate line connector and a common signal wire formed on a substrate. A gate insulating layer may be formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer may be sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad, a data line connector and a pixel electrode may be formed thereon. The thickness of the data wire and the pixel electrode may be equal to or less than 500 ?.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 ?. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode and a gate pad, and a common signal wire including a plurality of common electrodes and a common signal line connecting the common electrodes are formed on a substrate. A first data pattern including a first data line defining a pixel region along with the gate line, a source and drain electrode, a first data pad and a pixel wire parallel to the common electrodes is formed on a gate insulating layer covering the gate wire and the common signal wire. A second data pattern including a second data line, a second data pad and a supplementary gate pad, which are connected to the first data line, the first data pad and the gate pad respectively through contact holes formed in a passivation layer, is on the passivation layer. Here, the first or the second data line and the common electrodes adjacent thereto overlap each other to prevent the light leakage near the edges of the pixel region and to increase the aperture ratio of the LCD.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode, a gate pad and a gate line connector and a common signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common signal wire. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain electrode, a data line, a data pad and a data line connector and a pixel electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed.

Abstract: A gate wire including a gate line, a gate electrode and a gate pad, and a common signal wire including a plurality of common electrodes and a common signal line connecting the common electrodes are formed on a substrate. A first data pattern including a first data line defining a pixel region along with the gate line, a source and drain electrode, a first data pad and a pixel wire parallel to the common electrodes is formed on a gate insulating layer covering the gate wire and the common signal wire. A second data pattern including a second data line, a second data pad and a supplementary gate pad, which are connected to the first data line, the first data pad and the gate pad respectively through contact holes formed in a passivation layer, is on the passivation layer. Here, the first or the second data line and the common electrodes adjacent thereto overlap each other to prevent the light leakage near the edges of the pixel region and to increase the aperture ratio of the LCD.