Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.

Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.

Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.

Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.

Abstract: A semiconductor package according to an embodiment includes a semiconductor chip having a first surface in which a chip pad is formed, a first insulating layer arranged on the first surface of the semiconductor chip and including a first filler, a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer, a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer, a second insulating layer contacting the redistribution pattern on the first insulating layer and including a second filler, a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer, an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer, and an external connection terminal electrically connected to the UBM.