Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.

Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.

Abstract: Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.

Abstract: A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Abstract: An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut.

Abstract: An electrical testing method for a semiconductor package for detecting defects of sockets mounted on a device under test (DUT) board is provided. A tester performs electrical test, accumulates electrical test results, and compares the accumulated results to reference values. The result of the comparison decides whether a plurality of sockets mounted on the DUT board can be used or not. The decision results are transmitted to a handler so that the socket having the defects is not used on the DUT board.

Abstract: A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Abstract: A method for testing semiconductor devices includes loading a customer tray with semiconductor devices to be tested. Groups of devices are transferred from the customer tray to buffer trays for testing. The number of devices in the customer tray is checked after each transfer. If the customer tray is empty, the number of semiconductor devices in the buffer trays is counted and compared with the number of semiconductor devices that can be tested simultaneously, typically either 64 or 128. If the number of semiconductor devices in the buffer trays is greater than the tester capacity, the semiconductor devices in at least one buffer tray are tested. If the number of semiconductor devices in the buffer trays is smaller than the tester capacity, semiconductor devices that were determined to be low quality in a prior test are loaded into a buffer tray, thus testing both untested and low quality devices together.

Abstract: A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.