Patents by Inventor Kyeong-Tae Lee

Kyeong-Tae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955318
    Abstract: A method for recovering ashing rate in a plasma processing chamber includes positioning a substrate in a processing volume of a processing chamber, wherein the substrate has a silicon chloride residue formed thereon. The method further includes evaporating the silicon chloride residue from the substrate. The method further includes depositing the evaporated silicon chloride on one or more interior surfaces in the processing volume. The method further includes exposing the deposited silicon chloride to an oxidizing environment to convert the deposited silicon chloride to a silicon oxide passivation layer. The oxidizing environment can comprise an oxygen-containing plasma, oxygen radicals, or a combination thereof.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yongkwan Kim, Changhun Lee, Kyeong-Tae Lee, Chung Hoan Kim, Youngmin Shin
  • Publication number: 20230290508
    Abstract: A method of providing information to predict the prognosis of breast reconstruction surgery and a system for predicting the prognosis of breast reconstruction surgery is provided. By using a method or system for providing information to predict the prognosis of breast reconstruction surgery according to one specific example, it is possible to predict the occurrence of complications in a subject into which a tissue expander is inserted or scheduled to be inserted during a process of breast reconstruction surgery and to prepare appropriate treatment for the subject, and it is possible to provide information to aid in selecting a type of tissue expander with a low possibility of complication occurrence.
    Type: Application
    Filed: February 3, 2023
    Publication date: September 14, 2023
    Inventor: Kyeong Tae LEE
  • Publication number: 20230290507
    Abstract: A method of providing information for predicting the prognosis of breast reconstruction surgery and a system for predicting the prognosis of breast reconstruction surgery is provided. By using the method or system for providing information for predicting the prognosis of breast reconstruction surgery according to one specific example of the present invention, it is possible to predict the possibility of implant rupture in a subject who has undergone or is scheduled to undergo two-stage breast reconstruction surgery, and it is possible to prepare an appropriate treatment according to this prediction, and to adjust the interval between breast reconstruction surgeries so as to lower the possibility of implant rupture. In addition, it is possible to provide information so that an implant with a low possibility of rupture may be selected.
    Type: Application
    Filed: February 3, 2023
    Publication date: September 14, 2023
    Inventor: Kyeong Tae LEE
  • Publication number: 20220293395
    Abstract: A method for recovering ashing rate in a plasma processing chamber includes positioning a substrate in a processing volume of a processing chamber, wherein the substrate has a silicon chloride residue formed thereon. The method further includes evaporating the silicon chloride residue from the substrate. The method further includes depositing the evaporated silicon chloride on one or more interior surfaces in the processing volume. The method further includes exposing the deposited silicon chloride to an oxidizing environment to convert the deposited silicon chloride to a silicon oxide passivation layer.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Yongkwan KIM, Changhun LEE, Kyeong-Tae LEE, Chung Hoan KIM, Youngmin SHIN
  • Patent number: 11031233
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 8, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Publication number: 20200013610
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Patent number: 10460921
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 29, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Patent number: 8956500
    Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: February 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Stephen Yuen, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
  • Publication number: 20130319614
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Patent number: 8529776
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: September 10, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Publication number: 20130029490
    Abstract: A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Inventors: Kyeong Tae Lee, Sang Wook Kim, Daehee Weon, Sang-jun Choi, Sreekar Bhaviripudi, Jahyong Kuh
  • Patent number: 7771606
    Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: August 10, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Patent number: 7754610
    Abstract: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: July 13, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Kyeong-Tae Lee, Jinhan Choi, Bi Jang, Shashank C. Deshmukh, Meihua Shen, Thorsten B. Lill, Jae Bum Yu
  • Patent number: 7737042
    Abstract: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: June 15, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Patent number: 7718538
    Abstract: A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 18, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorov, Shashank C. Deshmukh
  • Publication number: 20080264904
    Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.
    Type: Application
    Filed: April 24, 2007
    Publication date: October 30, 2008
    Inventors: STEPHEN YUEN, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
  • Publication number: 20080206900
    Abstract: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 28, 2008
    Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Publication number: 20080206901
    Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 28, 2008
    Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
  • Publication number: 20080197110
    Abstract: A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 21, 2008
    Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorov, Shashank C. Deshmukh
  • Patent number: 7368392
    Abstract: A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: May 6, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Jinhan Choi, Shashank Deshmukh, Sang Yi, Kyeong-Tae Lee