Patents by Inventor Kyeongran Yoo

Kyeongran Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SMART VERIFY ALGORITHM FOR IMPROVING RELIABILITY FOR ULTRA HIGH-PERFORMANCE 3D NAND
    Publication number: 20250061955
    Abstract: Methods and systems for an improved smart verify operation are disclosed herein. For example, a smart verify operation is performed on a wordline to acquire programming voltage information. Further, programming of the wordline is continued based on the programming voltage information acquired during the smart verify operation.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kyeongran Yoo, Henry Chin
  • SYSTEMS AND METHODS TO AVOID OVER PROGRAMMING AT INFREQUENT SMART VERIFY ACQUISITION FOR HIGH-PERFORMANCE 3D NAND
    Publication number: 20240428871
    Abstract: A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 26, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kyeongran Yoo, Henry Chin, Hua-Ling Hsu, Yanwei He
  • Method for controlling critical dimensions during an etch process
    Publication number: 20050064714
    Abstract: A method for controlling dimensions of structures formed on a substrate using an etch process includes measuring pre-etch dimensions of the respective elements of a patterned etch mask and adjusting a process recipe of the etch process using the results of the pre-etch measurements. In one application, the method is used to control critical dimensions of a gate structure of a field effect transistor.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 24, 2005
    Inventors: David Mui, Wei Liu, Hiroki Sasano, Kyeongran Yoo