Abstract: An array substrate of a display device includes an active area with curved corner portions and a compensation unit to reduce a difference in a parasitic capacitance of each gate line and each data line. Also, a plurality of data lines disposed to overlap the corner portions of the active area may be disposed with a different width therebetween to reduce a difference in parasitic capacitance of each gate line or data line disposed to overlap the corner portions of the active area and to reduce a resistance difference between data lines. Therefore, a degree of delay of a signal transferred through a plurality of gate lines or data lines can be similar in each gate line or data line, so that a defect can be prevented in a displayed image.

Abstract: Provided are an array substrate and a display device including the same. According to an exemplary embodiment of the present disclosure, if an active area has curved corner portions, a compensation unit configured to a parasitic capacitance is included. Further, a plurality of data lines disposed to overlap the corner portions of the active area is disposed with a different width therebetween. Therefore, it is possible to reduce a difference in parasitic capacitance of each gate line or data line disposed to overlap the corner portions of the active area and also possible to reduce a resistance difference between data lines. Therefore, a degree of delay of a signal transferred through a plurality of gate lines or data lines is similar in each gate line or data line, so that a defect does not occur in a displayed image.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.

Abstract: An array substrate for LCD devices and a method of manufacturing the same are provided. By using a structure where an empty space is secured in a data line area as in a DRD structure in which the number of data lines is reduced by half, a capacitance is sufficiently secured by forming a sub storage capacitor in the data line area of the empty space, and thus, an area of a main storage capacitor can be reduced. Accordingly, the cost can be reduced, and moreover, an aperture ratio can be enhanced.