Patents by Inventor Kyle Arrington
Kyle Arrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12685218Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.Type: GrantFiled: March 31, 2022Date of Patent: July 14, 2026Assignee: Intel CorporationInventors: Kyle Arrington, Kuang Liu, Bohan Shan, Hongxia Feng, Don Douglas Josephson, Stephen Morein, Kaladhar Radhakrishnan
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Publication number: 20260090427Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Srinivas Venkata Ramanuja PIETAMBARAM, Rui ZHANG, Mohit GUPTA
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Publication number: 20260090430Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Haobo CHEN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Ziyin LIN, Srinivas Venkata Ramanuja PIETAMBARAM
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Publication number: 20260090433Abstract: 3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Applicant: Intel CorporationInventors: Zhixin Xie, Mohamed Saber, Bohan Shan, Anastasia Arrington, Clay Arrington, Jigneshkumar Patel, Catherine Mau, Ryan Carrazzone, Haobo Chen, Wei Li, Kyle Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Hiroki Tanaka, Brandon Marin, Jeremy Ecton, Benjamin Duong, Gang Duan, Srinivas Pietambaram, Praveen Sreeramagiri, Andrew Jimenez, Yekan Wang, Jung Kyu Han
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Publication number: 20260090429Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.Type: ApplicationFiled: September 26, 2024Publication date: March 26, 2026Inventors: Bohan SHAN, Wei LI, Ryan CARRAZZONE, Jose WAIMIN, Kyle ARRINGTON, Haobo CHEN, Dingying David XU, Hongxia FENG, Yiqun BAI, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Benjamin DUONG, Gang DUAN, Srinivas Venkata Ramanuja PIETAMBARAM, Clay ARRINGTON
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Publication number: 20250218999Abstract: Embodiments disclosed herein include passive electrical components with thickness modifications. In an embodiment, such an apparatus may comprise a first substrate with a first material composition, where the first substrate comprises a passive electrical device. In an embodiment, a second substrate is coupled to the first substrate, where the second substrate has a second material composition. In an embodiment, a layer is over a surface of the second substrate opposite from the first substrate, and the layer is electrically insulating.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Hongxia FENG, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Dingying David XU, Yongki MIN, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Wei LI, Ashay DANI, Leonel R. ARANA, Brandon C. MARIN, Clay ARRINGTON, Hiroki TANAKA, Haobo CHEN, Mohit GUPTA
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Publication number: 20250218906Abstract: Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Zhixin XIE, Ziqing HAN, Srinivas Venkata Ramanuja PIETAMBARAM, Jung Kyu HAN, Gang DUAN, Yingying ZHANG, Minglu LIU, Manni MO, Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Ryan CARRAZZONE, Yiqun BAI, Ziyin LIN, Jose WAIMIN, Dingying David XU, Hongxia FENG, Yongki MIN, Brandon C. MARIN
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Publication number: 20250220818Abstract: Embodiments disclosed herein include an apparatus with a component embedded in a core. Apparatuses disclosed herein may comprise a first component with a first surface and a second surface opposite from the first surface, where a pad is provided on the first surface. In an embodiment, a layer is over the second surface of the first component, and a second component is over the layer. In an embodiment, the second component comprises a hole that passes through at least a partial thickness of the second component.Type: ApplicationFiled: December 27, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Wei LI, Jose WAIMIN, Ryan CARRAZZONE, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Haobo CHEN, Dingying David XU, Yongki MIN, Clay ARRINGTON, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Xiaoying GUO
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Publication number: 20250218998Abstract: Embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. In an embodiment, an array of interconnects is provided between the first substrate and the second substrate. The array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Shripad GOKHALE, Rui ZHANG, Mine KAYA, Haobo CHEN, Steve S. CHO, Timothy GOSSELIN, Kartik SRINIVASAN, Edvin CETEGEN, Kyle ARRINGTON, Nicholas S. HAEHN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Ashay DANI, Yoshihiro TOMITA, Ziyin LIN, Yiqun BAI, Jose WAIMIN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Jung Kyu HAN, Liang HE
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Publication number: 20250219028Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Jeremy Ecton, Bohan Shan, Numair Ahmed, Nevin Erturk, Ziyin Lin, Ryan Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Kyle Arrington, Jose Waimin, Srinivas Pietambaram, Gang Duan, Dingying Xu, Mohit Gupta, Brandon Marin, Xiaoying Guo, Clay Arrington
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Patent number: 12349303Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.Type: GrantFiled: February 22, 2023Date of Patent: July 1, 2025Assignee: Intel CorporationInventors: Karumbu Meyyappan, Kyle Arrington, David Craig, Pooya Tadayon
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Publication number: 20250191998Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: ApplicationFiled: February 13, 2025Publication date: June 12, 2025Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
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Publication number: 20250192059Abstract: Embodiments disclosed herein include bridge structures for package substrates. In an embodiment, a package substrate comprises a substrate that is a dielectric material. In an embodiment, a cavity is formed into the substrate. A first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. In an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Brandon C. MARIN, Minglu LIU, Bohan SHAN, Bainye Francoise ANGOUA, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Numair AHMED, Jeremy D. ECTON, Benjamin DUONG, Hongxia FENG, Bai NIE, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Andrey GUNAWAN, Yingying ZHANG, Yosuke KANAOKA, Yosef KORNBLUTH, Aaditya Anand CANDADAI, Daniel ROSALES-YEOMANS, Jieying KONG, Shuqi LAI, Ao WANG, Joshua STACEY, Dilan SENEVIRATNE, Jade Sharee LEWIS
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Publication number: 20250183180Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.Type: ApplicationFiled: December 5, 2023Publication date: June 5, 2025Inventors: Brandon C. MARIN, Robert Alan MAY, Minglu LIU, Bohan SHAN, Jason M. GAMBA, Lilia MAY, Tarek A. IBRAHIM, Hiroki TANAKA, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD, Benjamin DUONG, Haobo CHEN, Xiao LIU, Xiyu HU, Wei WEI, Bai NIE, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Yiqun BAI
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Publication number: 20250112085Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
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Publication number: 20250112164Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Patent number: 12266589Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: GrantFiled: April 15, 2024Date of Patent: April 1, 2025Assignee: Intel CorporationInventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
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Publication number: 20250106983Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
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Patent number: 12238892Abstract: A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment, the two-phase immersion cooling system may include a low boiling point liquid including at least two liquids that are substantially immiscible with one another.Type: GrantFiled: December 21, 2020Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Raanan Sover, James Williams, Bradley Smith, Nir Peled, Paul George, Jason Armstrong, Alexey Chinkov, Meir Cohen, Je-Young Chang, Kuang Liu, Ravindranath Mahajan, Kelly Lofgreen, Kyle Arrington, Michael Crocker, Sergio Antonio Chan Arguedas
