Patents by Inventor Kyle Arrington
Kyle Arrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240112971Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
-
Patent number: 11923268Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.Type: GrantFiled: February 4, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington
-
Publication number: 20240071848Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
-
First-level integration of second-level thermal interface material for integrated circuit assemblies
Patent number: 11881438Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.Type: GrantFiled: January 17, 2020Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Elah Bozorg-Grayeli, Kyle Arrington, Sergio Chan Arguedas, Aravindha Antoniswamy -
Patent number: 11854935Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: GrantFiled: February 19, 2020Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Weston Bertrand, Kyle Arrington, Shankar Devasenathipathy, Aaron McCann, Nicholas Neal, Zhimin Wan
-
Patent number: 11842944Abstract: An integrated circuit (IC) assembly comprising an IC die and a frame material that has been dispensed over the assembly substrate to be further adjacent to a perimeter edge of the IC die. The frame material may be selected to have flow properties that minimize slump, for example so a profile of a transverse cross-section through the frame material may retain convex curvature. The frame material may be cured following dispense, and upon application of a thermal interface material (TIM), the frame material may and act as a barrier, impeding flow of the TIM. The frame material may be compressed by force applied through an external thermal solution, such as a heat sink, to ensure good contact to the TIM.Type: GrantFiled: December 26, 2019Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Kyle Arrington, Frederick Atadana, Taylor Gaines, Minseok Ha
-
Patent number: 11832419Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.Type: GrantFiled: December 20, 2019Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
-
Publication number: 20230317706Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Kyle ARRINGTON, Kuang LIU, Bohan SHAN, Hongxia FENG, Don Douglas JOSEPHSON, Stephen MOREIN, Kaladhar RADHAKRISHNAN
-
Publication number: 20230290661Abstract: The present disclosure relates to a tray assembly. The tray assembly may include a die transport tray. The die transport tray may include an inner bottom surface for accommodating a plurality of dies. The tray assembly may further include a lid. The lid may include an inner top surface, wherein the inner top surface of the lid may face the inner bottom surface of the die transport tray when the lid is assembled over the die transport tray. The lid may further include a shock absorbing material on the inner top surface for contacting the plurality of dies, if present.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Kyle ARRINGTON, Kirk WHEELER, Emily SCHUBERT, Dingying XU, Bassam ZIADEH
-
Publication number: 20230209759Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Inventors: Karumbu MEYYAPPAN, Kyle ARRINGTON, David CRAIG, Pooya TADAYON
-
Publication number: 20230128903Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
-
Patent number: 11622466Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.Type: GrantFiled: June 15, 2020Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Karumbu Meyyappan, Kyle Arrington, David Craig, Pooya Tadayon
-
Patent number: 11616000Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.Type: GrantFiled: June 25, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
-
Publication number: 20220199489Abstract: Embodiments disclosed herein include polymer thermal interface materials. In an embodiment a thermal interface material (TIM) comprises a polymer matrix and a liquid metal filler in the polymer matrix. In an embodiment, the liquid metal filler comprises a liquid core and an oxide layer around the liquid core. In an embodiment, the liquid core comprises gallium or a gallium alloy, and the oxide layer comprises a metal oxide other than gallium oxide.Type: ApplicationFiled: December 15, 2021Publication date: June 23, 2022Inventors: Kyle ARRINGTON, Kosuke HIROTA, Elah BOZORG-GRAYELI
-
Publication number: 20220201889Abstract: A two-phase immersion cooling system for an integrated circuit assembly may be formed utilizing boiling enhancement structures formed on or directly attached to heat dissipation devices within the integrated circuit assembly, formed on or directly attached to integrated circuit devices within the integrated circuit assembly, and/or conformally formed over support devices and at least a portion of an electronic board within the integrated circuit assembly. In still a further embodiment, the two-phase immersion cooling system may include a low boiling point liquid including at least two liquids that are substantially immiscible with one another.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Raanan Sover, James Williams, Bradley Smith, Nir Peled, Paul George, Jason Armstrong, Alexey Chinkov, Meir Cohen, Je-Young Chang, Kuang Liu, Ravindranath Mahajan, Kelly Lofgreen, Kyle Arrington, Michael Crocker, Sergio Antonio Chan Arguedas
-
Publication number: 20210392774Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Karumbu MEYYAPPAN, Kyle ARRINGTON, David CRAIG, Pooya TADAYON
-
Publication number: 20210327782Abstract: Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Dong-Ho Han, Jaejin Lee, Jerrod Peterson, Kyle Arrington
-
Publication number: 20210272885Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and an interposer over the package substrate. In an embodiment, the interposer comprises a ceramic. In an embodiment, the electronic package further comprises a first die over the interposer and a second die over the interposer. In an embodiment, the first die and the second die are electrically coupled together by the interposer. In an embodiment, the electronic package further comprises an integrated heat spreader (IHS) over the first die and the second die.Type: ApplicationFiled: February 27, 2020Publication date: September 2, 2021Inventors: Kyle ARRINGTON, Aaron MCCANN, Weston K. BERTRAND
-
Publication number: 20210257277Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Inventors: Weston BERTRAND, Kyle ARRINGTON, Shankar DEVASENATHIPATHY, Aaron MCCANN, Nicholas NEAL, Zhimin WAN
-
Publication number: 20210242105Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Applicant: INTEL CORPORATIONInventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington