Abstract: Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

Abstract: Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

Abstract: An example computing system includes: a processing system, a hardware accelerator coupled to the processing system, and a software platform executing on the processing system. The hardware accelerator includes: a programmable integrated circuit (IC) configured with an acceleration circuit having a static region and a programmable region; a memory in the programmable IC configured to store metadata describing interface circuitry in at least one of the static region and the programmable region of the acceleration circuit. The software platform includes program code executable by the processing system to read the metadata from the memory of the hardware accelerator.

Abstract: System and method generally relate to protection of a bussed network. In such a system, an access controller is configured for bussed communication via a communication bus to obtain a current transaction. An interface firewall is coupled for bussed communication with the access controller and configured to check for a fault associated with a transfer. A data processing device is coupled for communication with the interface firewall and configured to execute the current transaction to provide the transfer for the interface firewall. The interface firewall is configured to detect the fault associated with the transfer, to block access to the data processing device associated with the fault, and to communicate a blocked status for the data processing device.

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

Abstract: A method of circuit design can include detecting, using a processor, a transactional inefficiency within trace data including transactions involving a first circuit block of a circuit design and, in response to the detecting, generating a modified version of the circuit design by including a transaction converter circuit block within the circuit design. The transaction converter circuit block can be coupled to the first circuit block and can be adapted to correct the transactional inefficiency.

Abstract: A method of enabling a simulation of a circuit design is described. The method comprises generating, using a computer, an initial representation of the circuit design; simulating the circuit design using the initial representation by driving input signals to the circuit design based upon a simulation event listing; capturing event data associated with a plurality of timestamps in a first file while simulating the circuit design; identifying a plurality of events associated with a timestamp of a plurality of timestamps; reordering events of the plurality of associated with the timestamp; and generating a replay module used to drives input signals to the circuit design. A system for enabling a simulation of a circuit design is also described.

Abstract: Various example implementations are directed to methods and systems for simulating circuit designs having configuration parameters. According to one example implementation, code blocks of a circuit design for which execution of operations described by the code blocks is conditioned on a value of one or more of a set of configuration parameters, are identified. For each identified code block, a respective expression is determined that indicates whether or not the code block will be executed for different sets of values of the set of configuration parameters. The circuit design is simulated for a first set of values for the configuration parameters. The simulation is performed using a model that omits code blocks that describe sets of operations that will not be executed. The determined expressions are evaluated to determine whether or not each identified code block was realized in the simulation model.

Abstract: Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.

Abstract: Approaches for testing a module of a circuit design include tagging flip-flops in a netlist of the module with respective path names of the flip-flops from a hardware description language specification of the module. In simulating with the netlist, event data are captured to a first file. A process determines whether or not event data in the first file matches event data in a second file of event data. In response to a difference determined between the first file and the second file, an earliest occurrence of an event in the first file having an associated signal value of a first signal that does not match an associated signal value of a corresponding event in the second file is determined. The one of the plurality of flip-flops that output the first signal is determined, and the respective path name of the one flip-flop is output.

Abstract: Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.

Abstract: Methods for generating a circuit design are disclosed. A plurality of cells is instantiated in the circuit design in response to user input. The set of interface parameters of each cell is arranged into a hierarchy of interface levels as indicated by an interface model corresponding to the cell. For each of the interface levels, values of the sets of interface parameters of cells included in the interface level are respectively propagated to other cells directly connected to the cell. In response to propagating a value of an interface parameter from another cell of the plurality of cells to the cell and the cell having a value of the corresponding interface parameter that is different from the propagated value, a value for the corresponding interface parameter of the cell is determined using a respective propagation function associated with the corresponding interface level.