Patents by Inventor Kyle J. Arrington

Kyle J. Arrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250219021
    Abstract: In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Ziyin Lin, Ryan Joseph Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Yiqun Bai, Kyle J. Arrington, Jose Fernando Waimin Almendares, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Brandon Christian Marin, Clay Bradley Arrington, Yongki Min, Joseph Allen Van Nausdle, Joseph F. Walczyk, Pooya Tadayon, Mohamed R. Saber
  • Publication number: 20250218904
    Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Bohan Shan, Kyle J. Arrington, Ryan Joseph Carrazzone, Jose Fernando Waimin Almendares, Hongxia Feng, Srinivas Venkata Ramanuja Pietambaram, Hiroki Tanaka, Haobo Chen, Gang Duan, Brandon Christian Marin, Yongki Min, Dingying Xu, Clay Bradley Arrington, Jeremy D. Ecton, Suddhasattwa Nad
  • Publication number: 20250218964
    Abstract: Technologies for connected components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Kyle J. Arrington, Bohan Shan, Ryan Joseph Carrazzone, Jose Fernando Waimin Almendares, Dingying Xu, Hiroki Tanaka, Ziyin Lin, Yiqun Bai, Hongxia Feng, Yongki Min, Mohit Gupta, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Clay Bradley Arrington
  • Publication number: 20240186227
    Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Kyle J. Arrington, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Hongxia Feng, Xiaoying Guo, Ziyin Lin, Brandon Christian Marin, Srinivas V. Pietambaram, Dingying Xu
  • Publication number: 20240186228
    Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Kyle J. Arrington, Yiqun Bai, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Hongxia Feng, Xiaoying Guo, Ziyin Lin, Brandon Christian Marin, Bai Nie, Srinivas V. Pietambaram, Dingying Xu
  • Patent number: 11869824
    Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Kyle J. Arrington, Aaron McCann, Kelly Lofgreen, Elah Bozorg-Grayeli, Aravindha Antoniswamy, Joseph B. Petrini
  • Publication number: 20240006400
    Abstract: In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Kyle J. Arrington, Karumbu Nathan Meyyappan, Srikant Nekkanty
  • Publication number: 20230197565
    Abstract: A thermal management solution in a mobile computing system is bonded to an integrated circuit component by a thermal interface material layer (TIM layer) that does not require the application of a permanent force to ensure a reliable thermally conductive connection. A leaf spring or other loading mechanism that can apply a permanent force to a TIM layer can be secured to a printed circuit board by fasteners that extend through holes in the board in the vicinity of the integrated circuit component. These holes consume area that could otherwise be used for signal routing. In devices that use a TIM layer that does not require the application of a permanent force, the thermal management solution can be attached to a printed circuit board or chassis at a location remote to the integrated circuit component, where the attachment mechanism does not or minimally interferes with integrated circuit component signal routing.
    Type: Application
    Filed: December 28, 2022
    Publication date: June 22, 2023
    Inventors: Jerrod P. Peterson, Kyle J. Arrington, Ellann Cohen, Mark A. MacDonald, Christopher Michael Moore, Akhilesh P. Rallabandi
  • Publication number: 20210134698
    Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Kyle J. Arrington, Aaron McCann, Kelly Lofgreen, Elah Bozorg-Grayeli, Aravindha Antoniswamy, Joseph B. Petrini
  • Publication number: 20210125896
    Abstract: A thermal interface material may be formed comprising a liquid metal and a corrosion resistant filler material. The thermal interface material may be used in an integrated circuit assembly between at least one integrated circuit device and a heat dissipation device, wherein the corrosion resistant filler material changes the physical properties of the thermal interface material, which may prevent failure modes from occurring during the operation of the integrated circuit assembly and may assist in maintaining a bond line thickness between the at least one integrated circuit device and the heat dissipation device.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Kyle J. Arrington, Aaron Mccann, Kelly Lofgreen, Aravindha R. Antoniswamy, Shankar Devasenathipathy