Patents by Inventor Kyle Johns
Kyle Johns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190378704Abstract: A method of forming a capillary tube for electrospray ionization (ESI) having at least one tip with a desired tip profile. The method includes providing a pre-finished capillary tube of substantially homogenous material. The capillary tube has a first end and an internal bore. The first end of the pre-finished capillary tube is wet-etched in an etchant for an etch duration. A protective fluid flows through the internal bore of the capillary tube at a flow rate during the etch duration and the flow rate and the etch duration are determined to obtain the desired tip profile below a liquid level of the etchant.Type: ApplicationFiled: June 6, 2019Publication date: December 12, 2019Inventors: Kyle John James Bachus, Herbert Tze Cheung Foo, Heike Ebendorff-Heidepriem, Yvonne Marie Stokes, Josef Adam Giddings
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Patent number: 10350042Abstract: A vaginal insert which can be provided in an applicator for the treatment of urinary incontinence in females. The vaginal insert can provide tension-free incontinence treating support perpendicularly to the urethra (i.e., across the urethra).Type: GrantFiled: July 25, 2014Date of Patent: July 16, 2019Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Kyle John Schuman, Steven Charles Schapel, Amanda R. Altan, Michael Andrew Maloney, Sean Michael Maloney, Yogesh Kumar Chauhan
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Patent number: 10242280Abstract: A system and method provide for determining regions of interest within an image based on viewer interaction with the image. At least one image associated with a location is provided for display in a viewport, and pose data related to user interaction with the at least one image is identified. Weights are assigned to portions of the at least one image based on the pose data, the weights indicating at least a period of time the portion of the at least one image is generally at a center of the viewport. Based on the assigned weights, image regions of interest of the at least one image are determined.Type: GrantFiled: November 7, 2017Date of Patent: March 26, 2019Assignee: Google LLCInventors: Kyle John Krafka, Alan Sheridan
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Patent number: 10215657Abstract: A weight applicator system includes a shaft, an applicator assembly, and a weight feed assembly. The shaft defines a length between a proximal end and a distal end configured to support a wheel-tire assembly for common rotation about a longitudinal axis of the shaft. The applicator assembly is supported by the shaft and includes a base portion disposed upon the shaft and operable to translate axially along the length of the shaft, a radial portion connected to the base portion and operable to radially move relative to the base portion between a retracted position and an extended position; and a pressure roller rotatably supported by the radial portion about an axis of rotation. The weight feed assembly is operable to feed a prescribed length of weighted material to the pressure roller.Type: GrantFiled: March 30, 2016Date of Patent: February 26, 2019Assignee: Android Industries LLCInventors: Donald Graham Straitiff, Barry Allan Clark, David Henry Larson, Daniel David Larson, Kyle John Swinter, Lawrence J. Lawson
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Patent number: 10149374Abstract: A target material receptacle includes a structure including a passageway that extends in a first direction, the passageway configured to receive target material that travels along a target material path; and a deflector system configured to receive target material from the passageway. The deflector system includes a plurality of deflector elements. Each deflector element is oriented at a first acute angle relative to a direction of travel of an instance of the target material that travels along the target material path, and each deflector element in the deflector system is separated from a nearest deflector element by a distance along a second direction that is different from the first direction.Type: GrantFiled: August 25, 2017Date of Patent: December 4, 2018Assignee: ASML Netherlands B.V.Inventors: Armin Bernhard Ridinger, Kyle John Scaffidi, Michael Arthur Perry, Jr.
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Publication number: 20180322800Abstract: A system for providing interaction between a virtual human and a user, the system comprising: a tangible interface providing a physical interface between the user and the virtual human, an imaging system directed towards the physical interface to provide images of the user interacting with the tangible interface; a tracking system tracking at least one position or the user; a microphone capturing speech from the user; a simulation system receiving inputs from the tangible interface, the imaging system, the tracking system and the microphone, the simulation system generating output signals corresponding to the virtual human; and a display presenting the output signals to the user.Type: ApplicationFiled: April 30, 2018Publication date: November 8, 2018Applicants: University of Florida Research Foundation, Incorporated, Augusta University Research Institute, Inc.Inventors: Benjamin Chak Lum Lok, David Scott Lind, Juan Carlos Cendan, Andrew Brian Raij, Brent H. Rossen, Aaron Andrew Kotranza, Kyle John Johnsen
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Patent number: 10037280Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.Type: GrantFiled: May 29, 2015Date of Patent: July 31, 2018Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Meghal Varia, Serag Gadelrab, Muhammad Umar Choudry
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Patent number: 10019380Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.Type: GrantFiled: September 25, 2015Date of Patent: July 10, 2018Assignee: QUALCOMM IncorporatedInventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh
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Patent number: 10007619Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.Type: GrantFiled: September 20, 2015Date of Patent: June 26, 2018Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Alexander Miretsky, Meghal Varia, Kyle John Ernewein, Manokanthan Somasundaram, Muhammad Umar Choudry, Serag Monier Gadelrab
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Publication number: 20180157926Abstract: A system and method provide for determining regions of interest within an image based on viewer interaction with the image. At least one image associated with a location is provided for display in a viewport, and pose data related to user interaction with the at least one image is identified. Weights are assigned to portions of the at least one image based on the pose data, the weights indicating at least a period of time the portion of the at least one image is generally at a center of the viewport. Based on the assigned weights, image regions of interest of the at least one image are determined.Type: ApplicationFiled: November 7, 2017Publication date: June 7, 2018Inventors: Kyle John Krafka, Alan Sheridan
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Patent number: 9978288Abstract: A system for providing interaction between a virtual human and a user, the system comprising: a tangible interface providing a physical interface between the user and the virtual human, an imaging system directed towards the physical interface to provide images of the user interacting with the tangible interface; a tracking system tracking at least one position or the user; a microphone capturing speech from the user; a simulation system receiving inputs from the tangible interface, the imaging system, the tracking system and the microphone, the simulation system generating output signals corresponding to the virtual human; and a display presenting the output signals to the user.Type: GrantFiled: February 11, 2010Date of Patent: May 22, 2018Assignees: University of Florida Research Foundation, Inc., Augusta University Research Institute, Inc.Inventors: Benjamin Chak Lum Lok, David Scott Lind, Juan Carlos Cendan, Andrew Brian Raij, Brent H. Rossen, Aaron Andrew Kotranza, Kyle John Johnsen
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Patent number: 9842268Abstract: A system and method provide for determining regions of interest within an image based on viewer interaction with the image. At least one image associated with a location is provided for display in a viewport, and pose data related to user interaction with the at least one image is identified. Weights are assigned to portions of the at least one image based on the pose data, the weights indicating at least a period of time the portion of the at least one image is generally at a center of the viewport. Based on the assigned weights, image regions of interest of the at least one image are determined.Type: GrantFiled: March 24, 2016Date of Patent: December 12, 2017Assignee: Google LLCInventors: Kyle John Krafka, Alan Sheridan
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Patent number: 9824015Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: November 21, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Patent number: 9792215Abstract: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.Type: GrantFiled: March 28, 2015Date of Patent: October 17, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Meghal Varia, Serag Gadelrab
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Patent number: 9785559Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Patent number: 9747213Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.Type: GrantFiled: May 29, 2015Date of Patent: August 29, 2017Assignee: QUALCOMM IncorporatedInventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
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Publication number: 20170091116Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh
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Publication number: 20160350225Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Inventors: Jason Edward PODAIMA, Paul Christopher John WIERCIENSKI, Kyle John ERNEWEIN, Carlos Javier MOREIRA, Meghal VARIA, Serag GADELRAB, Muhammad Umar CHOUDRY
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Patent number: D798923Type: GrantFiled: November 3, 2016Date of Patent: October 3, 2017Inventor: Kyle John Homola
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Patent number: D814349Type: GrantFiled: October 25, 2015Date of Patent: April 3, 2018Inventor: Kyle John Ettinger