Abstract: A receiver circuit for a sensor includes a photosensitive input circuit and a logarithmic-signal circuit including a PN junction coupled to a pulse voltage node. The pulse voltage node may be coupled to the P-type terminal of the PN junction and an output of the photosensitive input circuit. In some examples, the receiver circuit also may include a linear-signal circuit and/or a square-root-signal circuit.

Abstract: A receiver circuit for a sensor includes a photosensitive input circuit and a logarithmic-signal circuit including a PN junction coupled to a pulse voltage node. The pulse voltage node may be coupled to the P-type terminal of the PN junction and an output of the photosensitive input circuit. In some examples, the receiver circuit also may include a linear-signal circuit and/or a square-root-signal circuit.

Abstract: A differential data transmitter with pre-emphasis comprises a main driver coupled to receive an input data stream and to produce a main differential output stream which varies with the input stream, circuitry which provides a delayed and inverted version of the input stream, and a first pre-emphasis driver coupled to the output of the circuitry and arranged to produce a pre-emphasis differential output stream which varies with the delayed and inverted input stream. The pre-emphasis differential output stream is coupled to the main differential output stream to produce differential data transmitter output signals. The main and pre-emphasis drivers operate in parallel, with the pre-emphasis driver boosting the output signals when consecutive bits in the input stream change state, and attenuating the output signals when consecutive bits in the input stream do not change state.

Abstract: A differential data transmitter with pre-emphasis comprises a main driver coupled to receive an input data stream and to produce a main differential output stream which varies with the input stream, circuitry which provides a delayed and inverted version of the input stream, and a first pre-emphasis driver coupled to the output of the circuitry and arranged to produce a pre-emphasis differential output stream which varies with the delayed and inverted input stream. The pre-emphasis differential output stream is coupled to the main differential output stream to produce differential data transmitter output signals. The main and pre-emphasis drivers operate in parallel, with the pre-emphasis driver boosting the output signals when consecutive bits in the input stream change state, and attenuating the output signals when consecutive bits in the input stream do not change state.

Abstract: A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal Vin, a sample-and-hold stage which receives Vin and outputs sampled signal Vin,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, Vin,samp is compared with a threshold voltage Vthresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to Vin,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to Vin,samp.