Patents by Inventor Kyle McPherson

Kyle McPherson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10361095
    Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Young-Joon Park, Kyle McPherson
  • Publication number: 20190074193
    Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.
    Type: Application
    Filed: May 16, 2018
    Publication date: March 7, 2019
    Inventors: Abbas ALI, Dhishan KANDE, Qi-Zhong HONG, Young-Joon PARK, Kyle MCPHERSON
  • Patent number: 10002774
    Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is<the first temperature. After the annealing, a pattern is formed on the metal interconnect layer, and at least the metal interconnect layer is etched.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 19, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Young-Joon Park, Kyle McPherson