Abstract: A retractable cover system may include a cover adapted to cover an object, a holder, and a retraction cord arranged to pull the cover into the holder when the cover is not in use, wherein the cover, the holder and the retraction cord are arranged to cause the cover to collapse as it is pulled into the holder. The cover may include a retraction channel, and the holder may include a storage sleeve. The retraction channel may be arranged to collapse the cover in response to pulling the retraction cord by gathering the cover as the cover is pulled into the storage sleeve by the retraction cord.

Abstract: A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.

Abstract: For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask in such a way that all the edges are printed by the phase shift mask.

Abstract: A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.

Abstract: A method is provided for making an integrated circuit. Cell representing a layout of a set of features, is divided into at least a first region and a second region. Optical Proximity Correction is carried out on at least the first region of cell. One or more instances of cell are located to define IC prior to carrying out final OPC optimisation on the second regions of each cell in the defined IC.

Abstract: In an immersion lithography method, the photoresist layer is provided with a shield layer to protect it from degradation caused by contact with the immersion liquid. The shield layer is transparent at the exposure wavelength and is substantially impervious to the immersion liquid. The shield layer can be formed of a material which can be removed using the same developer as is used to develop the photoresist layer after exposure.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Abstract: In the fabrication of semiconductor devices using the PECVD process to deposit hardmask material such as amorphous carbon, structure and process are described for reducing migration of species from the amorphous carbon which can damage an overlying photoresist. In one embodiment useful to 248 nm and 193 nm photolithography exposure wavelengths, amorphous carbon is plasma-deposited on a substrate to pre-defined thickness and pre-defined optical properties. A SiON layer is combined with a silicon-rich oxide layer, a silicon-rich nitride layer or a TEOS layer to create a capping layer resistant to species-migration. Layers are formulated to pre-determined thicknesses, refractive indices and extinction coefficients. The capping stacks constitute an effective etch mask for the amorphous carbon; and the hardmask properties of the amorphous carbon are not compromised. The disclosure has immediate application to fabricating polysilicon gates.

Abstract: An original layout of an integrated circuit is modified using optical proximity correction (OPC) to obtain a second layout. During OPC, a sensitivity to flare for each feature is conveniently identified. To map the flare, the amplitude of intensity is mapped over a field of exposure, which is typically a rectangle-shaped area corresponding to an exposure of a stepper. The field of exposure is divided into regions in which a region is characterized as having substantially the same amplitude throughout. For each feature a decision is made whether to make a further correction or not. If correction is desired, the amount of correction is based in part on the region in which the feature is located and the sensitivity of the feature. This same approach is applicable to other properties than flare that vary based on the location within the field of exposure.

Abstract: For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask in such a way that all the edges are printed by the phase shift mask.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift, layer that helps, in combination with the organic ARC, to reduce undesired reflection.