Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Abstract: An apparatus for synchronizing sets of data words rendered by a plurality of asynchronous data renderers includes a plurality of data registers, each data register receiving and temporarily storing a word of data in a first set of data words, from a corresponding one of the plurality of asynchronous data renderers. In addition, the apparatus includes a controller that prevents each asynchronous data renderer from transferring a word of data, in a second set of data words, to its corresponding data register when the corresponding data register is storing its word of data, in the first set of data words. Further, the controller, when each of the plurality of data registers has received its word of data for the first set of data words, controls the plurality of data registers to output a synchronized set of data words.

Abstract: A method and apparatus is provided for processing vector primitives with interleaved frame buffer controllers. Each frame buffer controller includes an edge stepper, a span stepper, and a pixel processor. Each edge stepper provides pixel data for multiple pixels during each clock cycle. Any pixels not in an area of the display assigned to a frame buffer controller are discarded without further processing. Pixels which are in the areas assigned the frame buffer controller are further processed. Additionally, two vectors may be processed simultaneaously by the edge steppers.

Abstract: In a computer graphics system, per vertex depth cue scale factor values and depth cue rendering parameters are determined for the vertices of a triangle to be displayed. Interpolation circuitry determines a per pixel depth cue scale factor and per pixel color values for each of the pixels in the triangle. When the computer graphics system includes texture mapping hardware, a blending circuit combines the per pixel color values and the texture mapped color values to provide per pixel resulting color values. The per pixel depth cue scale factor value, the per pixel resulting color values and a depth cue color are used to determine per pixel depth cued color values for each of the pixels in the triangle. Accurate depth cueing is achieved with or without texture mapping.