Patents by Inventor Kyle W. Terrill
Kyle W. Terrill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7795675Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench.Type: GrantFiled: September 21, 2005Date of Patent: September 14, 2010Assignee: Siliconix IncorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
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Patent number: 7435650Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.Type: GrantFiled: June 21, 2004Date of Patent: October 14, 2008Assignee: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
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Patent number: 7291884Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.Type: GrantFiled: June 4, 2003Date of Patent: November 6, 2007Assignee: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
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Patent number: 7268032Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.Type: GrantFiled: September 21, 2005Date of Patent: September 11, 2007Assignee: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
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Patent number: 7045857Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.Type: GrantFiled: March 26, 2004Date of Patent: May 16, 2006Assignee: Siliconix IncorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi, Qufei Chen
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Publication number: 20040227182Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.Type: ApplicationFiled: June 21, 2004Publication date: November 18, 2004Applicant: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
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Publication number: 20040038467Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance.Type: ApplicationFiled: June 4, 2003Publication date: February 26, 2004Applicant: Siliconix incorporatedInventors: Mohamed N. Darwish, Kyle W. Terrill, Jainhai Qi
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Patent number: 6350645Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.Type: GrantFiled: July 22, 1997Date of Patent: February 26, 2002Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Kyle W. Terrill
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Patent number: 6100128Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated.Type: GrantFiled: August 4, 1998Date of Patent: August 8, 2000Assignee: Integrated Device Technology, Inc.Inventors: Pailu Wang, Chuen-Der Lien, Kyle W. Terrill
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Patent number: 5831899Abstract: A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated.Type: GrantFiled: April 7, 1997Date of Patent: November 3, 1998Assignee: Integrated Device Technology, Inc.Inventors: Pailu Wang, Chuen-Der Lien, Kyle W. Terrill
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Patent number: 5745404Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.Type: GrantFiled: December 5, 1995Date of Patent: April 28, 1998Assignee: Integrated Device Technology, In.cInventors: Chuen-Der Lien, Kyle W. Terrill
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Patent number: 5712508Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.Type: GrantFiled: December 5, 1995Date of Patent: January 27, 1998Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Kyle W. Terrill
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Patent number: 5574305Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.Type: GrantFiled: July 8, 1994Date of Patent: November 12, 1996Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Kyle W. Terrill
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Patent number: 5393677Abstract: A first process embodiment of the present invention comprises the steps of implanting a blanket low dose n-well implant before field oxidation. A blanket n-type punchthrough suppression implant precedes the field oxidation step. After field oxidation, an implantation masking step is used to adjust the doping for the p-well in its active and field regions.Type: GrantFiled: February 19, 1993Date of Patent: February 28, 1995Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Kyle W. Terrill, Jeong Y. Choi
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Patent number: 5289027Abstract: A submicron MOSFET is fabricated on an ultrathin layer with a generally intrinsic channel having a dopant concentration less than about 10.sup.16 cm.sup.-3. The channel thickness is preferably no greater than about 0.2 microns; the ratio of channel thickness to length is less than about 1:4, and preferably no greater than about 1:2. Punchthrough and other short-channel effects are inhibited by the application of an appropriate back-gate voltage, which may also be varied to adjust the voltage threshold.Type: GrantFiled: September 28, 1992Date of Patent: February 22, 1994Assignee: Hughes Aircraft CompanyInventors: Kyle W. Terrill, Prahalad K. Vasudev
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Patent number: 5258317Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.Type: GrantFiled: February 13, 1992Date of Patent: November 2, 1993Assignee: Integrated Device Technology, Inc.Inventors: Chuen-Der Lien, Kyle W. Terrill
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Patent number: H707Abstract: A method for preventing latch-up in an integrated circuit structure, and in particular, in a CMOS structure, includes the use of a high-energy blanket or maskless ion implant that reduces the substrate resistance by creating a highly ion doped buried layer in the semiconductor device. The thickness and the positioning of the heavily doped layer can be accurately ascertained through the ion implantation process. The transition region between the highly doped buried layer and the lightly doped substrate is sharper, and thus the suppression of latch-up is more effective than in prior devices fabricated with prior techniques. An increase in the holding and critical currents is found, due to the reduced substrate resistance.Type: GrantFiled: June 8, 1987Date of Patent: November 7, 1989Assignee: The United States of America as represented by the Secretary of the NavyInventors: Chemning Hu, Kyle W. Terrill