Patents by Inventor Kyle YEN

Kyle YEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lock detector and method of detecting lock status for phase lock loop
    Patent number: 8456207
    Abstract: A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng Wei Kuo, Kyle Yen, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
  • LOCK DETECTOR AND METHOD OF DETECTING LOCK STATUS FOR PHASE LOCK LOOP
    Publication number: 20130120035
    Abstract: A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei KUO, Kyle YEN, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU