Patents by Inventor Kyo-Min Sohn

Kyo-Min Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529395
    Abstract: A memory cell array may include a normal cell array and a spare cell array, the normal cell array having a plurality of normal memory cells connected to normal lines and the spare memory cell array having a plurality of spare memory cells connected to spare lines configured to replace a failed normal memory cell with a spare memory cell. A spare line address encoding circuit may be configured to generate a spare line address which encodes spare line enable signals being applied when a spare line replacing a normal line is activated to indicate a physical location of the spare line being activated. A spare line adjacent address generator may be configured to generate spare line adjacent address based on the spare line address, and to activate spare lines physically adjacent to the activated spare line.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyo Min Sohn, Dong Su Lee, Young Jin Cho, Hyung Woo Choi
  • Patent number: 10468092
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-ho Hyun, Kyo-min Sohn, Je-min Ryu, Ho-Seok Seol
  • Patent number: 10347355
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Publication number: 20190206460
    Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.
    Type: Application
    Filed: July 11, 2018
    Publication date: July 4, 2019
    Inventors: Seong IL O, Jun Hyung KIM, Kyo Min SOHN
  • Publication number: 20190198087
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-ho HYUN, Kyo-min Sohn, Je-min Ryu, Ho-Seok Seol
  • Patent number: 10296414
    Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon Shin, Hae-Suk Lee, Han-Vit Jung, Kyo-Min Sohn
  • Publication number: 20190130991
    Abstract: A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 2, 2019
    Inventors: Jong-Pil SON, Kyo-Min SOHN
  • Patent number: 10242731
    Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-ho Hyun, Kyo-min Sohn, Je-min Ryu, Ho-Seok Seol
  • Publication number: 20180322005
    Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Applicant: Samsung Electronics Co. , Ltd.
    Inventors: Sang-Hoon SHIN, Hae-Suk LEE, Han-Vit JUNG, Kyo-Min SOHN
  • Patent number: 10014037
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyo-min Sohn
  • Patent number: 9941247
    Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N?1).
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-Suk Lee, Kyo-Min Sohn, Ho-Young Song, Sang-Hoon Shin, Han-Vit Jung
  • Publication number: 20180075889
    Abstract: A memory cell array may include a normal cell array and a spare cell array, the normal cell array having a plurality of normal memory cells connected to normal lines and the spare memory cell array having a plurality of spare memory cells connected to spare lines configured to replace a failed normal memory cell with a spare memory cell. A spare line address encoding circuit may be configured to generate a spare line address which encodes spare line enable signals being applied when a spare line replacing a normal line is activated to indicate a physical location of the spare line being activated. A spare line adjacent address generator may be configured to generate spare line adjacent address based on the spare line address, and to activate spare lines physically adjacent to the activated spare line.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 15, 2018
    Inventors: Kyo Min Sohn, Dong Su Lee, Young Jin Cho, Hyung Woo Choi
  • Publication number: 20180068742
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: October 27, 2017
    Publication date: March 8, 2018
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 9859022
    Abstract: A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-joong Kim, Soo-hyeong Kim, Sang-hoon Shin, Ju-yun Jung, Ho-young Song, Kyo-min Sohn, Hae-suk Lee, Bu-il Jung, Han-vit Jeong
  • Patent number: 9858981
    Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Young Lee, Kyo-Min Sohn, Sang-Joon Hwang, Sung-Min Seo, Sang-Bo Lee, Nak-Won Heo
  • Patent number: 9831003
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Publication number: 20170315860
    Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon SHIN, Hae-Suk LEE, Han-Vit JUNG, Kyo-Min SOHN
  • Publication number: 20170229192
    Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
    Type: Application
    Filed: April 27, 2017
    Publication date: August 10, 2017
    Inventors: Kyo-Min Sohn, Ho-Young Song, Sang-Joon Hwang, Cheol Kim, Dong-Hyun Sohn
  • Patent number: 9727409
    Abstract: A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon Shin, Hae-Suk Lee, Han-Vit Jung, Kyo-Min Sohn
  • Publication number: 20170221534
    Abstract: A semiconductor memory device includes a plurality of memory banks in a first region, a data terminal to which an input data signal is input, the data terminal being in a second region, and an inverting circuit that inverts or non-inverts the input data signal in response to an inversion control signal indicating whether the input data signal has been inverted, wherein at least one inverting circuit is disposed for each of the plurality of memory banks.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Inventor: Kyo-min SOHN