Patents by Inventor KYO-WOOK LEE

KYO-WOOK LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055482
    Abstract: A semiconductor device including: first and second cell regions; a substrate including first and second surfaces; first to third active patterns extending in a first horizontal direction in the first cell region, the first to third active patterns spaced apart from each other in a second horizontal direction; a fourth active pattern extending in the first horizontal direction in the second cell region, the fourth active pattern is aligned with the second active pattern in the first horizontal direction; an active cut separating the second and fourth active patterns; a source/drain region on the second active pattern; a buried rail extending in the first horizontal direction on the second surface of the substrate, the first buried rail overlaps each of the second and fourth active patterns in a vertical direction; and a source/drain contact penetrating the substrate and second active pattern and connecting the source/drain region to the buried rail.
    Type: Application
    Filed: March 31, 2023
    Publication date: February 15, 2024
    Inventors: Seok Hyeon YOON, Kyo-Wook LEE, Seung Hun LEE, Seung Han PARK
  • Patent number: 10170472
    Abstract: A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Lak Gyo Jeong, Yong Rae Cho, Kyo Wook Lee, Hee Bum Hong
  • Publication number: 20180040616
    Abstract: A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.
    Type: Application
    Filed: June 26, 2017
    Publication date: February 8, 2018
    Inventors: Lak Gyo Jeong, Yong Rae Cho, Kyo Wook Lee, Hee Bum Hong
  • Patent number: 9780097
    Abstract: A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyo-Wook Lee, Dong-Hun Lee, Hee-Bum Hong, Yong-Rae Cho
  • Publication number: 20160190141
    Abstract: A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 30, 2016
    Inventors: KYO-WOOK LEE, Dong-Hun Lee, Hee-Bum Hong, Yong-Rae Cho