Patents by Inventor Kyo Yeon CHO

Kyo Yeon CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910400
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Woo Park, Kyo Yeon Cho
  • Publication number: 20190326323
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Applicant: SK hynix Inc.
    Inventors: Min Woo PARK, Kyo Yeon CHO
  • Patent number: 10388661
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Woo Park, Kyo Yeon Cho
  • Publication number: 20180175053
    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the same. The method of manufacturing the semiconductor device may include forming a tunnel insulating layer in a channel hole passing through a preliminary stack structure in which interlayer insulating layers and material layers are alternately stacked. The method may include forming recess areas by removing the material layers exposed through a slit passing through the preliminary stack structure. The method may include forming a data storage layer in the recess areas through the slit. The thickness of the data storage layer may be formed regardless of a size of the channel hole.
    Type: Application
    Filed: August 21, 2017
    Publication date: June 21, 2018
    Applicant: SK hynix Inc.
    Inventors: Min Woo PARK, Kyo Yeon CHO