Patents by Inventor Kyoichi Nagata
Kyoichi Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134596Abstract: The content output device includes an information acquisition unit, a content generation unit and an output unit. The information acquisition unit acquires driving state information which is information related to a current driving state of a vehicle. The content generation unit acquires one or more content elements corresponding to a trigger condition, from among a plurality of content elements combinable with each other, when the driving state information satisfies the trigger condition, and generates an output content using the acquired content elements. The output unit outputs the output content.Type: ApplicationFiled: June 29, 2021Publication date: April 25, 2024Inventors: Takashi IIZAWA, Keita KURAMOCHI, Atsuhiro YAMANAKA, Hideki NAGATA, Kazuaki TANAKA, Kyoichi TERAO, Takashi KAMIMURA, Daiki WAGURI, Yuya ISHIZAKI, Kei SUZUKI, Takayuki SHIMAZU
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Publication number: 20240071472Abstract: An apparatus that includes a sense amplifier including first and second cross-coupled transistors to amplify a potential difference between first and second digit lines, a compensation circuit configured to compensate a threshold difference between the first and second transistors, first and second local I/O lines coupled to the first and second digit lines, respectively, and an equalizing circuit configured to equalize the first and second local I/O lines. The equalizing circuit is configured to change a precharge level of the first and second local I/O lines from a first potential to a second potential before a compensation operation of the compensation circuit is completed.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Applicant: MICRON TECHNOLOGY, INC.Inventor: KYOICHI NAGATA
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Patent number: 11915779Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: GrantFiled: March 2, 2022Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20220383912Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: ApplicationFiled: March 2, 2022Publication date: December 1, 2022Inventor: Kyoichi Nagata
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Patent number: 11289151Abstract: Compensation for threshold voltage mismatches in cross-coupled pairs of transistors and related systems, devices, and methods are disclosed. An apparatus includes a cross-coupled pair of transistors, and a compensation pair of transistors. The cross-coupled pair of transistors includes a first transistor and a second transistor. A first gate of the first transistor is coupled to a first bit line and a second gate of the second transistor coupled to a second bit line. The compensation pair of transistors includes a third transistor and a fourth transistor. The third transistor is coupled in series with the first transistor between a first source of the first transistor and a common source line. The fourth transistor is coupled in series with the second transistor between a second source of the second transistor and the common source line. A memory device includes the sense amplifier. A computing system includes the memory device.Type: GrantFiled: November 8, 2019Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Patent number: 11270740Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: GrantFiled: July 8, 2019Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20210142842Abstract: Compensation for threshold voltage mismatches in cross-coupled pairs of transistors and related systems, devices, and methods are disclosed. An apparatus includes a cross-coupled pair of transistors, and a compensation pair of transistors. The cross-coupled pair of transistors includes a first transistor and a second transistor. A first gate of the first transistor is coupled to a first bit line and a second gate of the second transistor coupled to a second bit line. The compensation pair of transistors includes a third transistor and a fourth transistor. The third transistor is coupled in series with the first transistor between a first source of the first transistor and a common source line. The fourth transistor is coupled in series with the second transistor between a second source of the second transistor and the common source line. A memory device includes the sense amplifier. A computing system includes the memory device.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventor: Kyoichi Nagata
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Patent number: 10916289Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for refreshing ferroelectric memory. An example apparatus includes: a word line; a first memory cell coupled to a first digit line and stores a first data on the first digit line responsive to the word line in an active state; a second memory cell coupled to a second digit line and stores a second data on the second digit line responsive to the word line in the active state. The first digit line is coupled to a first power potential and the second digit line is coupled to a second power potential in a refresh operation.Type: GrantFiled: August 15, 2019Date of Patent: February 9, 2021Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20190385650Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: ApplicationFiled: July 8, 2019Publication date: December 19, 2019Inventor: Kyoichi Nagata
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Publication number: 20190371385Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for refreshing ferroelectric memory. An example apparatus includes: a word line; a first memory cell coupled to a first digit line and stores a first data on the first digit line responsive to the word tine in an active state; a second memory cell coupled to a second digit line and stores a second data on the second digit line responsive to the word line in the active state. The first digit line is coupled to a first power potential and the second digit line is coupled to a second power potential in a refresh operation.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Applicant: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Patent number: 10490260Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.Type: GrantFiled: November 3, 2017Date of Patent: November 26, 2019Assignee: Micron Technology, Inc.Inventors: Kyoichi Nagata, Yuuji Motoyama
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Patent number: 10403347Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for refreshing ferroelectric memory. An example apparatus includes: a word line; a first memory cell coupled to a first digit line and stores a first data on the first digit line responsive to the word line in an active state; a second memory cell coupled to a second digit line and stores a second data on the second digit line responsive to the word line in the active state. The first digit line is coupled to a first power potential and the second digit line is coupled to a second power potential in a refresh operation.Type: GrantFiled: January 29, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Patent number: 10388335Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: GrantFiled: August 14, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20190237122Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for refreshing ferroelectric memory. An example apparatus includes: a word line; a first memory cell coupled to a first digit line and stores a first data on the first digit line responsive to the word line in an active state; a second memory cell coupled to a second digit line and stores a second data on the second digit line responsive to the word line in the active state. The first digit line is coupled to a first power potential and the second digit line is coupled to a second power potential in a refresh operation.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Applicant: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20190051335Abstract: A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.Type: ApplicationFiled: August 14, 2017Publication date: February 14, 2019Inventor: Kyoichi Nagata
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Publication number: 20180061480Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.Type: ApplicationFiled: November 3, 2017Publication date: March 1, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Kyoichi Nagata, Yuuji Motoyama
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Patent number: 9837139Abstract: A semiconductor device includes an equalizing circuit and a control circuit. The equalizing circuit executes an operation of pre-charging the signal input/output line pair used for data inputting/outputting and an operation of equalizing it independently of each other. In case a plurality of data write operations occur in succession, the control circuit halts pre-charge control in the equalizing circuit in the course of consecutive write operations.Type: GrantFiled: January 28, 2014Date of Patent: December 5, 2017Assignee: Micron Technology, Inc.Inventors: Kyoichi Nagata, Yuuji Motoyama
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Patent number: 9520177Abstract: A semiconductor device is equipped with memory cells which are provided at the intersections of word lines and local bit lines, hierarchical switches which are respectively connected between the local bit lines and a global bit line, and a hierarchical sense amplifier which amplifies a potential difference generated between signal nodes, with the signal nodes being respectively connected to the local bit lines. According to the present invention, because the hierarchical sense amplifier is a differential type circuit, a stable sensing operation can be performed. In addition, because one hierarchical sense amplifier can be assigned to multiple local bit lines, the number of hierarchical sense amplifiers can be reduced.Type: GrantFiled: November 5, 2013Date of Patent: December 13, 2016Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.Inventors: Yasuhiro Matsumoto, Kyoichi Nagata, Izumi Nakai
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Patent number: 9424222Abstract: Apparatuses and methods for charge sharing across data buses based on respective levels of the data buses are disclosed herein. An example apparatus may include a first bus, a second bus, and a charge sharing circuit coupled to each of the first bus and the second bus. The charge sharing circuit may be configured to couple the first bus to the second bus based on logic levels of the first bus and the second bus. For example, the charge sharing circuit may couple the first bus to the second bus responsive to the first bus and the second bus having inverted logic levels.Type: GrantFiled: September 8, 2015Date of Patent: August 23, 2016Assignee: Micron Technology, Inc.Inventor: Kyoichi Nagata
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Publication number: 20150302914Abstract: A semiconductor device is equipped with memory cells which are provided at the intersections of word lines and local bit lines, hierarchical switches which are respectively connected between the local bit lines and a global bit line, and a hierarchical sense amplifier which amplifies a potential difference generated between signal nodes, with the signal nodes being respectively connected to the local bit lines. According to the present invention, because the hierarchical sense amplifier is a differential type circuit, a stable sensing operation can be performed. In addition, because one hierarchical sense amplifier can be assigned to multiple local bit lines, the number of hierarchical sense amplifiers can be reduced.Type: ApplicationFiled: November 5, 2013Publication date: October 22, 2015Inventors: Yasuhiro Matsumoto, Kyoichi Nagata, Izumi Nakai