Abstract: Provided is a method of manufacturing a semiconductor device. the method comprises receiving layout data including a plurality of pieces of pattern data, the plurality of pieces of pattern data having through first to Nth unique patterns (N is a natural number greater than or equal to two), calculating first to Nth density values of the first to Nth unique patterns from the layout data and calculating first to Nth populations of the first to Nth unique patterns from the layout data, performing sampling by selecting some unique patterns among the first to Nth unique patterns, the selecting based on the first to Nth density values and the first to Nth populations, and performing etch modeling on sampled patterns of the plurality of pieces of pattern data, the sampled patterns corresponding to the selected unique patterns.

Abstract: One embodiment of the present invention relates to a system that calibrates a photolithography process model. During operation, the system receives a process model which models a photolithography process. The system further receives measured critical dimension (CD) values for a first set of features that were printed by applying the photolithography process to a layout. The system then calibrates the process model using the measured CD values so that CD values predicted by the process model substantially match the measured CD values, and depth of focus (DOF) values predicted by the process model for a second set of features are substantially maximized.