Abstract: A front end signal processing method and apparatus for processing a signal from an image sensor are provided for readily clamping a black level, improving the manufacturing yield, and reducing the power consumption. A luminance detector/digitizer receives a sensor output signal from an image sensor, detects luminance information included in the sensor output signal, and generates a digital luminance signal representative of the detected luminance information. A digital processor receives the digital luminance signal, and multiplies the digital luminance signal by a predetermined gain code to generate the multiplication result as a front end processed signal output. An optical black clamp receives the digital luminance signal from the luminance signal detector/digitizer and supplies a feedback signal produced from the digital luminance signal to the luminance signal detector/digitizer to clamp a black level of the luminance signal to a constant value.

Abstract: The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1˜k. Each sampling unit has input terminals 1-1˜k and output terminals 3-1˜k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1˜k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.

Abstract: The objective is to provide a sampling/holding circuit that can operate at high speed and low power consumption. The sampling/holding circuit has multiple sampling units 2-1˜k. Each sampling unit has input terminals 1-1˜k and output terminals 3-1˜k. The values received at the input terminals are sampled, and the sample values are accumulated. Also, the accumulated sample values are generated at output terminals 3-1˜k. One holding unit 6 has an input terminal 5 and an output terminal 7, which are shared by the multiple sampling units. By multiplexing the outputs of the multiple sampling units, multiplexing unit 4 connects any output to the input of holding unit 6. Holding unit 6 holds the sample value and generates it at output 7.

Abstract: A front end signal processing method and apparatus for processing a signal from an image sensor are provided for readily clamping a black level, improving the manufacturing yield, and reducing the power consumption. A luminance detector/digitizer receives a sensor output signal from an image sensor, detects luminance information included in the sensor output signal, and generates a digital luminance signal representative of the detected luminance information. A digital processor receives the digital luminance signal, and multiplies the digital luminance signal by a predetermined gain code to generate the multiplication result as a front end processed signal output. An optical black clamp receives the digital luminance signal from the luminance signal detector/digitizer and supplies a feedback signal produced from the digital luminance signal to the luminance signal detector/digitizer to clamp a black level of the luminance signal to a constant value.

Abstract: A digital-to-analog converter is provided which compensates for relative errors among weighting elements used for D/A conversion. The converter includes a decoder, a rotator, and a weighting section. The rotator receives decoded signals from a decoder to produce rotated output signals for activating or deactivating a plurality of weighting elements, respectively, included in the weighting section. The rotated output signals assure that the same number of weighting elements are activated in each of a plurality of sub-periods of time constituting a main period of time of the D/A conversion and that each of the plurality of weighting elements is activated the same number of times during the whole main period.

Abstract: An interpolation DAC includes first and second registers connected to receive the X least significant and Y most significant bits of a digital input word, and are clocked to latch the X least significant bits and Y most significant bits at a first clock rate. An adder has a first group of X inputs, a second group of X inputs, X outputs, and a carry output. A third register has X inputs, and X outputs coupled to the second group of X inputs of the adder. The third register is clocked to latch the outputs of the adder at a second clock rate which is the oversampling ratio times faster than the first clock rate. A Y bit plus 1 bit DAC in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register. The duplicate LSB is connected to receive the carry output from the adder. A low pass filter responsive to the Y bit plus 1 bit DAC produces an analog output representative of a value of the digital input word.

Abstract: A digital-to-analog converter converts a digital word of M+N bits to an analog signal with reduced bit switching error, by providing a first group of M input conductors conducting the M most significant bits of the digital word, a second group of N input conductors conducting the N least significant bits of the digital word, and an M bit plus 1 adder having M inputs connected to a corresponding conductor of the first group. A signal representative of the most significant bit of the digital input word is coupled to an input of the adder. The adder has M output conductors. Signals on the N input conductors of the second group together with signals on the M output conductors from an intermediate digital word of M+N bits differ in value from the first digital word. An M+N bit DAC receives the intermediate digital word and produces an analog current corresponding to the value of the intermediate digital word.