Patents by Inventor Kyoji Sato

Kyoji Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9720879
    Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shinichi Sutou, Ichiro Kasama, Kyoji Sato, Takashi Hanai, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda
  • Patent number: 8266416
    Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Limited
    Inventors: Koji Ishihara, Tetsuo Kawano, Kyoji Sato, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Masato Kondo
  • Publication number: 20110246747
    Abstract: A reconfigurable circuit includes a data execution unit including a plurality of execution elements, each of which performs execution with respect to plural data upon the plural data being all in a valid state, and holds valid-state output data indicative of a result of the execution at an output node while all the plural data are in the valid state, a data selecting unit configured to connect between the execution elements in a reconfigurable manner, and a data input unit configured to supply input data to a series of execution elements to perform a series of executions, wherein a valid or invalid state of given data is specified by a valid signal accompanying and forming a pair with the given data, and the input data supplied from the data input unit to the data execution unit are fixed to valid-state constant data while the series of executions are performed.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 6, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takashi HANAI, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda, Ichiro Kasama, Kyoji Sato, Shinichi Sutou
  • Publication number: 20110185152
    Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.
    Type: Application
    Filed: December 20, 2010
    Publication date: July 28, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinichi Sutou, Ichiro Kasama, Kyoji Sato, Takashi Hanai, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda
  • Publication number: 20090164773
    Abstract: A dynamic reconfiguration supporting method that generates a driver function to cause a dynamic reconfiguration circuit to execute a program of an application described in a predetermined language, includes acquiring a configuration defining file representing a configuration of a cluster of the dynamic reconfiguration circuit in execution of the process of the application, generating an address map representing an address of a processing element (to be referred to as “PE” hereinafter) in the cluster on the basis of the configuration defining file acquired by the acquiring operation, generating a driver function that associates the function and an address of the PE which executes the function with reference to the address map, when a PE which executes a function described in the application is allocated from the PE, and creating a driver function file that stores the driver function.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 25, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Koji ISHIHARA, Tetsuo Kawano, Kyoji Sato, Tsuguchika Tabaru, Manabu Matsuyama, Ryuichi Ohzeki, Masato Kondo