Abstract: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second STI regions arranged in a first direction, a first diffusion region having a first conductivity type surrounded by the first STI region, a second diffusion region having a second conductivity type surrounded by the second STI region, and a third diffusion region extending in a second direction such that the third diffusion region is arranged between the first and second STI regions; a first gate electrode including a first polycrystalline silicon film covering a part of the first diffusion region to form a P-channel MOS transistor; a second gate electrode including a second polycrystalline silicon film covering a part of the second diffusion region to form an N-channel MOS transistor; and a third polycrystalline silicon film extending in the second direction such that the third polycrystalline silicon film covers the third diffusion region.

Abstract: Disclosed herein is an apparatus that includes: a memory cell array including a plurality of first memory cell mats arranged in a first direction; a first voltage line supplied with a first voltage, the first voltage line extending in the first direction and being connected to a plurality of first vias each arranged over a corresponding one of even numbered ones of the plurality of first memory cell mats; and a second voltage line supplied with a second voltage different from the first voltage, the second voltage line extending in the first direction and being connected to a plurality of second vias each arranged over a corresponding one of odd numbered ones of the plurality of first memory cell mats.

Abstract: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second STI regions arranged in a first direction, a first diffusion region having a first conductivity type surrounded by the first STI region, a second diffusion region having a second conductivity type surrounded by the second STI region, and a third diffusion region extending in a second direction such that the third diffusion region is arranged between the first and second STI regions; a first gate electrode including a first polycrystalline silicon film covering a part of the first diffusion region to form a P-channel MOS transistor; a second gate electrode including a second polycrystalline silicon film covering a part of the second diffusion region to form an N-channel MOS transistor; and a third polycrystalline silicon film extending in the second direction such that the third polycrystalline silicon film covers the third diffusion region.

Abstract: Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

Abstract: Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.