Patents by Inventor Kyoko Kuroki

Kyoko Kuroki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147408
    Abstract: There are provided a phase shift mask having a small number of haze defects, that is, a phase shift mask capable of sufficiently suppressing occurrence of haze, and a method for manufacturing the phase shift mask. A phase shift mask (100) according to the present embodiment is a phase shift mask having a circuit pattern by application of exposure light having a wavelength of 200 nm or less, the phase shift mask including a substrate (11), a phase shift film (12) that is formed on the substrate (11) and has a circuit pattern, and a protective film (13) that is formed on an upper surface (12t) and a side surface (12s) of the phase shift film (12), in which the phase shift film (12) enables adjustment of each of phase and transmittance with respect to the exposure light to be transmitted to a predetermined extent, the protective film (13) has a refractive index n in a range of 1.2 or more and 2.6 or less with respect to the exposure light and an attenuation coefficient k in a range of 0.0 or more and 0.
    Type: Application
    Filed: January 30, 2023
    Publication date: May 8, 2025
    Inventors: Naoto YONEMARU, Kyoko KUROKI, Yosuke KOJIMA
  • Publication number: 20240419064
    Abstract: There are provided a phase shift mask having a small number of haze defects, that is, a phase shift mask capable of sufficiently suppressing occurrence of haze, and a method for manufacturing the phase shift mask.
    Type: Application
    Filed: January 30, 2023
    Publication date: December 19, 2024
    Inventors: Kyoko KUROKI, Kazuaki MATSUI, Yosuke KOJIMA, Naoto YONEMARU
  • Publication number: 20240302732
    Abstract: Provided are a phase shift mask blank that suppresses the formation of haze on a phase shift film surface and reduces film peeling during cleaning or a level difference in a cross-section of a modified portion during modification etching to improve transfer performance, a phase shift mask, and a method for manufacturing a phase shift mask.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 12, 2024
    Inventors: Kyoko KUROKI, Kazuaki MATSUI, Yosuke KOJIMA
  • Publication number: 20240152045
    Abstract: Provided are a phase shift mask blank that can sufficiently suppress the formation of haze on a phase shift film surface (on a phase mask), a phase shift mask having reduced haze defects, a method for manufacturing the phase shift mask, and a method for modifying the phase shift mask by electron beam modification etching.
    Type: Application
    Filed: March 3, 2022
    Publication date: May 9, 2024
    Inventors: Kazuaki MATSUI, Kyoko KUROKI, Yosuke KOJIMA
  • Publication number: 20230333461
    Abstract: There are provided a phase shift mask blank capable of sufficiently suppressing the generation of a haze on a mask, a phase shift mask with few haze defects, and a method for manufacturing the phase shift mask.
    Type: Application
    Filed: September 7, 2021
    Publication date: October 19, 2023
    Inventors: Kyoko KUROKI, Kazuaki MATSUI, Yosuke KOJIMA
  • Patent number: 11005065
    Abstract: A laminate includes: a substrate having a first surface and made of a high-molecular-weight material; an undercoat layer located on at least part of the first surface of the substrate and containing a first inorganic substance that has adsorption sites to be coupled to precursors serving as film-forming materials of an atomic layer deposition film; a functional layer located covering an outer surface of the undercoat layer and containing a second inorganic substance to be coupled to the adsorption sites of the undercoat layer, the functional layer being the atomic layer deposition film formed of the precursors; and an overcoat layer located covering an outer surface of the functional layer and containing a third inorganic substance.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 11, 2021
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Jin Sato, Mitsuru Kano, Hiroshi Koyama, Kyoko Kuroki
  • Publication number: 20180323401
    Abstract: A laminate includes: a substrate having a first surface and made of a high-molecular-weight material; an undercoat layer located on at least part of the first surface of the substrate and containing a first inorganic substance that has adsorption sites to be coupled to precursors serving as film-forming materials of an atomic layer deposition film; a functional layer located covering an outer surface of the undercoat layer and containing a second inorganic substance to be coupled to the adsorption sites of the undercoat layer, the functional layer being the atomic layer deposition film formed of the precursors; and an overcoat layer located covering an outer surface of the functional layer and containing a third inorganic substance.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 8, 2018
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Jin SATO, Mitsuru KANO, Hiroshi KOYAMA, Kyoko KUROKI
  • Publication number: 20140141218
    Abstract: A laminate body of the present invention includes a base material, an atomic layer deposition film that is formed along the outer surface of the base material, and an overcoat layer that covers the atomic layer deposition film with a film having a mechanical strength higher than that of the atomic layer deposition film.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Toshiaki Yoshihara, Kyoko Kuroki, Mitsuru Kano, Jin Sato
  • Publication number: 20080135981
    Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 12, 2008
    Applicant: LSI CORPORATION
    Inventors: Haruhiko Yamamoto, Hideaki Seto, Nobuyoshi Sato, Kyoko Kuroki
  • Patent number: 7371659
    Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 13, 2008
    Assignee: LSI Logic Corporation
    Inventors: Haruhiko Yamamoto, Hideaki Seto, Nobuyoshi Sato, Kyoko Kuroki
  • Patent number: 7201176
    Abstract: A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a second portion of the cleaning period. Residues left between the tips and the wafer edge areas during the first portion of the cleaning period are removed during the second portion. The change from the first group of tips to the second group of tips occurs while the wafer is rotating.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: April 10, 2007
    Assignee: LSI Logic Corporation
    Inventors: Kyoko Kuroki, Hideaki Seto
  • Publication number: 20060180176
    Abstract: A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a second portion of the cleaning period. Residues left between the tips and the wafer edge areas during the first portion of the cleaning period are removed during the second portion. The change from the first group of tips to the second group of tips occurs while the wafer is rotating.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 17, 2006
    Inventors: Kyoko Kuroki, Hideadki Seto
  • Patent number: 7056392
    Abstract: A wafer chuck is configured to hold a wafer efficiently for spin process cleaning of wafer edges and back sides. A first group of retractable tips extend to hold the wafer during a first portion of the cleaning period. A second group of retractable tips extend to hold the wafer during a second portion of the cleaning period. Residues left between the tips and the wafer edge areas during the first portion of the cleaning period are removed during the second portion. The change from the first group of tips to the second group of tips occurs while the wafer is rotating.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: June 6, 2006
    Assignee: LSI Logic Corporation
    Inventors: Kyoko Kuroki, Hideaki Seto