Patents by Inventor Kyoko SHOJI

Kyoko SHOJI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230259277
    Abstract: A memory system includes a nonvolatile memory and a serial peripheral interface (SPI) controller communicable with an external controller external to the memory system in accordance with an SPI standard, a first terminal through which the SPI controller receives a command, and a second terminal. The SPI controller is configured to operate in one of a plurality of operational modes in accordance with the command received through the first terminal. The operational modes include a first mode in which a signal received through the second terminal is used as a control signal to perform a predetermined function and a second mode in which the signal is not used as the control signal to perform the predetermined function.
    Type: Application
    Filed: August 26, 2022
    Publication date: August 17, 2023
    Inventors: Kiyotaka HAYASHI, Kyoko SHOJI
  • Patent number: 10884668
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroya Shirakura, Kyoko Shoji, Shinya Takeda
  • Publication number: 20200301610
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 24, 2020
    Inventors: Hiroya SHIRAKURA, Kyoko SHOJI, Shinya TAKEDA