Patents by Inventor Kyoko Tanimoto

Kyoko Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipeline system branch history table storing branch instruction addresses and target addresses with inhibit bits
    Patent number: 5732254
    Abstract: In an information processing apparatus, an instruction read inhibit bit is provided for branch instruction address and target instruction address registered in pair in the branch history. When the reading of a target instruction predicted from the pair of addresses is inhibited, the instruction read inhibit bit is set to an ON state. When execution of the predicted target instruction is canceled due to the difference between the predicted target instruction and an actual target instruction and the actual target instruction is read again, an instruction read inhibit bit setting section sets the instruction read inhibit bit of the pair of addresses in the branch history to the ON state.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: March 24, 1998
    Assignee: Fujitsu Limited
    Inventors: Kyoko Tanimoto, Aiichiro Inoue