Patents by Inventor Kyoko Tashima

Kyoko Tashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal
    Patent number: 7350062
    Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history).
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: March 25, 2008
    Assignee: Fujitsu Limited
    Inventors: Masaki Ukai, Kyoko Tashima, Aiichiro Inoue
  • Predicted return address selection upon matching target in branch history table with entries in return address stack
    Publication number: 20050278516
    Abstract: An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history).
    Type: Application
    Filed: August 22, 2005
    Publication date: December 15, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Masaki Ukai, Kyoko Tashima, Aiichiro Inoue
  • Predicted return address selection upon matching target in branch history table with entries in return address stack
    Patent number: 6530016
    Abstract: A pipeline process system, a super-scalar process system, or an out-of-order-execution process system is applied to an information processing device. A sequence of instructions containing a branch instruction, especially a subroutine, can be processed at a high speed using a branch history and a return address stack storing a return address corresponding to a subroutine call instruction. To successfully perform the process, when an instruction detected as a bit in the branch history is a subroutine return instruction, an address of a branched-to instruction registered in the branch history is compared with all return addresses stored in valid entries in the return address stack. A unit is provided to transmit a matching address as a return address of the return instruction to an instruction fetch unit for fetching an instruction.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: March 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Masaki Ukai, Kyoko Tashima, Aiichiro Inoue
  • Instruction controlling system and method thereof
    Patent number: 6016541
    Abstract: A general-purpose register address output from an instruction register is read and changed to a corresponding register update buffer address in an update table. Additionally, the update reservation instructing bit corresponding to the general-purpose register address is read out from a register update reservation table. If its value is "0", the general-purpose register address is provided to the general-purpose register, and the data stored at that address is input to an arithmetic unit. If the value of the bit is "1", the contents of the corresponding entry in the update table is registered to a reservation station. The reservation station determines the execution order of respective entries, and sequentially provides a register update buffer address to a register update buffer, and inputs the data stored at that address to the arithmetic unit.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: January 18, 2000
    Assignee: Fujitsu Limited
    Inventors: Kyoko Tashima, Takeo Asakawa, Aiichiro Inoue