Abstract: The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.