Patents by Inventor Kyoko Umeda

Kyoko Umeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160260795
    Abstract: In a semiconductor device including a nonvolatile memory, a novel stacked capacitive element is provided. The semiconductor device includes the stacked capacitive element including a first capacitive electrode made of an n-type well region formed in a semiconductor substrate, a second capacitive electrode formed so as to overlap the first capacitive electrode via a first capacitive insulating film, a third capacitive electrode formed so as to overlap the second capacitive electrode via a second capacitive insulating film, and a fourth capacitive electrode formed so as to overlap the third capacitive electrode via a third capacitive insulating film. To the first and third capacitive electrodes, a first potential is applied and, to the second and fourth capacitive electrodes, a second potential different from the first potential is applied.
    Type: Application
    Filed: January 11, 2016
    Publication date: September 8, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Satoshi Abe, Hiraku Chakihara, Kyoko Umeda, Yoshiyuki Kawashima, Kentaro Saito
  • Publication number: 20160204116
    Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.
    Type: Application
    Filed: March 17, 2016
    Publication date: July 14, 2016
    Inventors: Yoshiyuki Kawashima, Hiraku Chakihara, Kyoko Umeda, Akio Nishida
  • Patent number: 9324726
    Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: April 26, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Kawashima, Hiraku Chakihara, Kyoko Umeda, Akio Nishida
  • Publication number: 20160064402
    Abstract: In method for manufacturing a semiconductor device including a nonvolatile memory, a new method for manufacturing a capacitor element is provided. After working a control gate electrode, a gate insulation film including an electric charge accumulation section, and a memory gate electrode of a memory cell, in order to protect the memory cell, a p-type well of a MISFET is formed in a state the control gate electrode, the gate insulation film, and the memory gate electrode are covered by an insulation film. Also, this insulation film is used as a capacitor insulation film of a laminated type capacitor element.
    Type: Application
    Filed: August 19, 2015
    Publication date: March 3, 2016
    Inventors: Kyoko Umeda, Yoshiyuki Kawashima, Hiraku Chakihara
  • Publication number: 20160035734
    Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.
    Type: Application
    Filed: July 17, 2015
    Publication date: February 4, 2016
    Inventors: Yoshiyuki Kawashima, Hiraku Chakihara, Kyoko Umeda, Akio Nishida