Patents by Inventor Kyoman KANG
Kyoman KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240029814Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan PARK, Jinyoung KIM, Ilhan PARK, Kyoman KANG, Sangwan NAM
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Patent number: 11804280Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.Type: GrantFiled: May 20, 2022Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Kyoman Kang, Sangwan Nam
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Publication number: 20230104865Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.Type: ApplicationFiled: August 4, 2022Publication date: April 6, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Yongsung CHO, Minjae SEO, Kyoman KANG, Byungsoo KIM
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Patent number: 11600350Abstract: In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.Type: GrantFiled: October 25, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Seungbum Kim, Kyoman Kang
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Publication number: 20230055963Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.Type: ApplicationFiled: March 31, 2022Publication date: February 23, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yongsung CHO, Kyoman Kang, Minhwi Kim, Ilhan Park, Jinyoung Chun
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Publication number: 20220366993Abstract: In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.Type: ApplicationFiled: October 25, 2021Publication date: November 17, 2022Inventors: SEUNGBUM KIM, KYOMAN KANG
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Publication number: 20220277801Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan PARK, Jinyoung KIM, Ilhan PARK, Kyoman KANG, Sangwan NAM
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Patent number: 11386974Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.Type: GrantFiled: January 13, 2021Date of Patent: July 12, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Kyoman Kang, Sangwan Nam
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Publication number: 20220028478Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.Type: ApplicationFiled: January 13, 2021Publication date: January 27, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sehwan PARK, Jinyoung Kim, Ilhan Park, Kyoman Kang, Sangwan Nam
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Patent number: 10290343Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.Type: GrantFiled: May 30, 2017Date of Patent: May 14, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: ChaeHoon Kim, Kyoman Kang, Tae-Hong Kwon, Taeyun Lee, Jin-Young Chun
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Publication number: 20180096718Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.Type: ApplicationFiled: May 30, 2017Publication date: April 5, 2018Inventors: ChaeHoon KIM, Kyoman Kang, Tae-Hong Kwon, Taeyun Lee, Jin-Young Chun
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Patent number: 9576623Abstract: The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed.Type: GrantFiled: December 18, 2015Date of Patent: February 21, 2017Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seongook Jung, Hanwool Jeong, Young Hwi Yang, Kyoman Kang
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Patent number: 9552872Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.Type: GrantFiled: November 16, 2015Date of Patent: January 24, 2017Assignee: Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seongook Jung, Kyoman Kang, Hanwool Jeong, Young Hwi Yang, Juhyun Park
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Publication number: 20160181993Abstract: The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed.Type: ApplicationFiled: December 18, 2015Publication date: June 23, 2016Inventors: Seongook JUNG, Hanwool JEONG, Young Hwi YANG, Kyoman KANG
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Publication number: 20160141023Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.Type: ApplicationFiled: November 16, 2015Publication date: May 19, 2016Inventors: Seongook JUNG, Kyoman KANG, Hanwool JEONG, Young Hwi YANG, Juhyun PARK