Patents by Inventor Kyong-Ae Kim
Kyong-Ae Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8321633Abstract: A memory card, connected to a host, includes a NAND flash memory and a memory controller. The NAND flash memory includes multiple pages, and each page includes multiple sectors. The memory controller receives sector data and a corresponding sector address from the host. The memory controller enables the sector data to be transferred to the NAND flash memory over a first data bus, via a buffer memory, when the sector address is an address for accessing a first sector in a selected page. The memory controller enables the sector data to be transferred to the NAND flash memory over a second data bus, bypassing the buffer memory, when the sector address is an address for accessing a sector other than the first sector in the selected page.Type: GrantFiled: August 3, 2007Date of Patent: November 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Kyong-Ae Kim
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Patent number: 7894258Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.Type: GrantFiled: August 7, 2008Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Taek Jeong, Sang-Chul Kang, Kyong-Ae Kim
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Patent number: 7746703Abstract: A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.Type: GrantFiled: May 23, 2008Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-Ae Kim, Jin-Wook Lee, Yun-Ho Choi
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Patent number: 7672160Abstract: A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured to be programmed to one of a first, a second, or a third threshold voltage so that the first and second memory cells provide nine different threshold voltage combinations. The controller may be configured to provide a mapping of data of a set of three binary bits providing eight different data combinations to eight of the nine different threshold voltage combinations provided by the first and second memory cells. The controller may be further configured to write data of first, second, and third binary bits to the first and second memory cells by programming each of the first and second memory cells to a respective one of the first, second, or third threshold voltages using the mapping of data.Type: GrantFiled: January 19, 2007Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Min Gun Park, Kyong Ae Kim, Sang Won Hwang
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Patent number: 7555629Abstract: A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.Type: GrantFiled: December 30, 2005Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-Ae Kim, Jong-Yeol Park, Dong-Hee Lee
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Publication number: 20090147574Abstract: A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.Type: ApplicationFiled: August 7, 2008Publication date: June 11, 2009Inventors: Yong Taek Jeong, Sang-Chul Kang, Kyong-Ae Kim
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Patent number: 7529879Abstract: Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.Type: GrantFiled: November 16, 2004Date of Patent: May 5, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Hyuk Kim, Chan-Ik Park, Young-Gon Kim, Kyong-Ae Kim
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Publication number: 20090003064Abstract: A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.Type: ApplicationFiled: May 23, 2008Publication date: January 1, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyong-Ae KIM, Jin-Wook LEE, Yun-Ho CHOI
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Publication number: 20080195815Abstract: A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.Type: ApplicationFiled: February 4, 2008Publication date: August 14, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kyong-Ae KIM
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Patent number: 7356646Abstract: A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.Type: GrantFiled: December 28, 2004Date of Patent: April 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Kyong-Ae Kim
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Publication number: 20080034159Abstract: A memory card, connected to a host, includes a NAND flash memory and a memory controller. The NAND flash memory includes multiple pages, and each page includes multiple sectors. The memory controller receives sector data and a corresponding sector address from the host. The memory controller enables the sector data to be transferred to the NAND flash memory over a first data bus, via a buffer memory, when the sector address is an address for accessing a first sector in a selected page. The memory controller enables the sector data to be transferred to the NAND flash memory over a second data bus, bypassing the buffer memory, when the sector address is an address for accessing a sector other than the first sector in the selected page.Type: ApplicationFiled: August 3, 2007Publication date: February 7, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kyong-Ae Kim
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Publication number: 20070183197Abstract: A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured to be programmed to one of a first, a second, or a third threshold voltage so that the first and second memory cells provide nine different threshold voltage combinations. The controller may be configured to provide a mapping of data of a set of three binary bits providing eight different data combinations to eight of the nine different threshold voltage combinations provided by the first and second memory cells. The controller may be further configured to write data of first, second, and third binary bits to the first and second memory cells by programming each of the first and second memory cells to a respective one of the first, second, or third threshold voltages using the mapping of data.Type: ApplicationFiled: January 19, 2007Publication date: August 9, 2007Inventors: Min Gun Park, Kyong Ae Kim, Sang Won Hwang
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Publication number: 20060268609Abstract: A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.Type: ApplicationFiled: December 30, 2005Publication date: November 30, 2006Inventors: Kyong-Ae Kim, Jong-Yeol Park, Dong-Hee Lee
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Publication number: 20060004971Abstract: Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.Type: ApplicationFiled: November 16, 2004Publication date: January 5, 2006Inventors: Jin-Hyuk Kim, Chan-Ik Park, Young-Gon Kim, Kyong-Ae Kim
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Publication number: 20050207231Abstract: A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.Type: ApplicationFiled: December 28, 2004Publication date: September 22, 2005Inventor: Kyong-Ae Kim