Abstract: A display device includes a substrate, a display area disposed on the substrate and including a plurality of pixels and data lines, a peripheral area disposed outside the display area of the substrate, a pad portion disposed in the peripheral area, an encapsulation layer disposed in the peripheral area and the display area, and disposed on the plurality of pixels of the display area, a crack detection circuit disposed in the peripheral area, and a first crack detection line connected with the pad portion and the crack detection circuit. The first crack detection line is disposed on the encapsulation layer.

Abstract: Provided are semiconductor devices. A semiconductor device includes processors performing an operation using data stored in a memory; and a memory protector dividing the memory into a first window area and a second window area. The first window area including a first fragment page, which is of a first size. The second window area including a second fragment page, which is of a second size, wherein the second size is smaller than the first size. The memory protector configured to protect the first fragment page and the second fragment page from being accessed by the processors.

Abstract: A system on-chip includes a central processing unit and a memory controller. The memory controller receives initialization information indicating an initialization address range and an initialization value from the central processing unit, determines an initialization target memory and a local initialization address range of the initialization target memory based on the initialization information, and transmits initialization data including the initialization value to the initialization target memory by a predetermined unit to initialize the local initialization address range of the initialization target memory.

Abstract: Provided are semiconductor devices. A semiconductor device includes processors performing an operation using data stored in a memory; and a memory protector dividing the memory into a first window area and a second window area. The first window area including a first fragment page, which is of a first size. The second window area including a second fragment page, which is of a second size, wherein the second size is smaller than the first size. The memory protector configured to protect the first fragment page and the second fragment page from being accessed by the processors.

Abstract: A system on-chip includes a central processing unit and a memory controller. The memory controller receives initialization information indicating an initialization address range and an initialization value from the central processing unit, determines an initialization target memory and a local initialization address range of the initialization target memory based on the initialization information, and transmits initialization data including the initialization value to the initialization target memory by a predetermined unit to initialize the local initialization address range of the initialization target memory.

Abstract: A display controller is provided that includes a processing unit configured to process input data, a memory unit configured to store some of the processed input data before a transition signal is enabled, a memory management unit configured to map consecutive virtual addresses of an image displayed on a display panel to physical addresses of data stored in the memory unit, and a control unit configured to control the processing unit and the memory management unit in response to a control signal and configured to provide a range of virtual addresses designated by the transition signal in response to enablement of the transition signal such that the image is displayed on the display panel.

Abstract: An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption.

Abstract: An application processor includes a system memory unit, peripheral devices, a control unit and a central processing unit (CPU). The system memory unit includes one page table. The peripheral devices share the page table and perform a DMA (Direct Memory Access) operation on the system memory unit using the page table, where each of the peripheral devices includes a memory management unit having a translation lookaside buffer. The control unit divides a total virtual address space corresponding to the page table into sub virtual address spaces, assigns the sub virtual address spaces to the peripheral devices, respectively, allocates and releases a DMA buffer in the system memory unit, and updates the page table, where at least two of the sub virtual address spaces have different sizes from each other. The CPU controls the peripheral devices and the control unit. The application processor reduces memory consumption.

Abstract: A display controller is provided that includes a processing unit configured to process input data, a memory unit configured to store some of the processed input data before a transition signal is enabled, a memory management unit configured to map consecutive virtual addresses of an image displayed on a display panel to physical addresses of data stored in the memory unit, and a control unit configured to control the processing unit and the memory management unit in response to a control signal and configured to provide a range of virtual addresses designated by the transition signal in response to enablement of the transition signal such that the image is displayed on the display panel.