Patents by Inventor Kyong Hwan Koh
Kyong Hwan Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12132007Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: GrantFiled: January 31, 2023Date of Patent: October 29, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongwan Kim, Kyong Hwan Koh, Juhyeon Oh, Yongkwan Lee
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Publication number: 20240347401Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Inventors: KYONG HWAN KOH, JONGWAN KIM, JUHYEON OH, YONGKWAN LEE
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Patent number: 12057357Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.Type: GrantFiled: March 25, 2021Date of Patent: August 6, 2024Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Kyong Hwan Koh, Jongwan Kim, Juhyeon Oh, Yongkwan Lee
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Publication number: 20240178188Abstract: Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.Type: ApplicationFiled: August 1, 2023Publication date: May 30, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Myung-Sung KANG, Kyong Hwan KOH, Jin-Woo PARK, Chung Sun LEE, Hyeon Jun JIN
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Patent number: 11996365Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: GrantFiled: February 27, 2023Date of Patent: May 28, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongho Park, Seung Hwan Kim, Jun Young Oh, Kyong Hwan Koh, Sangsoo Kim, Dong-Ju Jang
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Publication number: 20230223347Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Inventors: JONGHO PARK, Seung Hwan Kim, Jung Young Oh, Kyong Hwan Koh, Sangsoo Kim, Dong-Ju Jang
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Publication number: 20230170310Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: ApplicationFiled: January 31, 2023Publication date: June 1, 2023Inventors: Jongwan KIM, Kyong Hwan KOH, Juhyeon OH, Yongkwan LEE
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Patent number: 11610845Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: GrantFiled: August 3, 2021Date of Patent: March 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongho Park, Seung Hwan Kim, Jun Young Oh, Kyong Hwan Koh, Sangsoo Kim, Dong-Ju Jang
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Patent number: 11581266Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: GrantFiled: March 25, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongwan Kim, Kyong Hwan Koh, Juhyeon Oh, Yongkwan Lee
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Publication number: 20220068835Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.Type: ApplicationFiled: March 25, 2021Publication date: March 3, 2022Inventors: Jongwan KIM, Kyong Hwan KOH, Juhyeon OH, Yongkwan LEE
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Publication number: 20220051957Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.Type: ApplicationFiled: March 25, 2021Publication date: February 17, 2022Inventors: KYONG HWAN KOH, JONGWAN KIM, JUHYEON OH, YONGKWAN LEE
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Publication number: 20210366832Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Inventors: JONGHO PARK, SEUNG HWAN KIM, JUN YOUNG OH, Kyong Hwan KOH, SANGSOO KIM, DONG-JU JANG
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Patent number: 11107769Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: GrantFiled: April 10, 2020Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongho Park, Seung Hwan Kim, Jun Young Oh, Kyong Hwan Koh, Sangsoo Kim, Dong-Ju Jang
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Publication number: 20210035913Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.Type: ApplicationFiled: April 10, 2020Publication date: February 4, 2021Inventors: JONGHO PARK, Seung Hwan Kim, Jun Young Oh, Kyong Hwan Koh, Sangsoo Kim, Dong-Ju Jang