Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.

Abstract: A method for preparing a zinc ferrite-based catalyst according to an embodiment of the present application comprises the steps of: contacting a metal precursor solution including a zinc precursor, a ferrite precursor, an acid solution and water with a basic aqueous solution to obtain a precipitate; and filtering and thereafter drying and calcining the precipitate, wherein the acid solution includes one or more of nitric acid (HNO3) and hydrocarbon acid.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture.

Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.

Abstract: A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

Abstract: A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.