Patents by Inventor Kyong-Mo Bang
Kyong-Mo Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230268300Abstract: A bonded structure can include a carrier including a first conductive contact and a second conductive contact, a first singulated element including a third conductive contact directly bonded to the first conductive contact without an adhesive, and a second singulated element including a fourth conductive contact directly bonded to the second conductive contact without an adhesive, wherein the first and second conductive contacts are spaced apart by a contact spacing of no more than 250 microns.Type: ApplicationFiled: February 23, 2023Publication date: August 24, 2023Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Gaius Gillman Fountain, Jr., Guilian Gao, Jeremy Alfred Theil, Gabriel Z. Guevara, Kyong-Mo Bang, Laura Wills Mirkarimi
-
Patent number: 10566310Abstract: A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.Type: GrantFiled: April 11, 2016Date of Patent: February 18, 2020Assignee: Invensas CorporationInventors: Belgacem Haba, Kyong-Mo Bang
-
Patent number: 10468380Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.Type: GrantFiled: March 5, 2018Date of Patent: November 5, 2019Assignee: Invensas CorporationInventors: Belgacem Haba, Kyong-Mo Bang
-
Publication number: 20180261571Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.Type: ApplicationFiled: March 5, 2018Publication date: September 13, 2018Applicant: Invensas CorporationInventors: Belgacem Haba, Kyong-Mo Bang
-
Patent number: 10026467Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.Type: GrantFiled: October 28, 2016Date of Patent: July 17, 2018Assignee: Invensas CorporationInventors: Zhuowen Sun, Yong Chen, Kyong-Mo Bang
-
Patent number: 10008469Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.Type: GrantFiled: November 21, 2016Date of Patent: June 26, 2018Assignee: Invensas CorporationInventors: Rajesh Katkar, Tu Tam Vu, Bongsub Lee, Kyong-Mo Bang, Xuan Li, Long Huynh, Gabriel Z. Guevara, Akash Agrawal, Willmar Subido, Laura Wills Mirkarimi
-
Patent number: 9928883Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.Type: GrantFiled: May 15, 2017Date of Patent: March 27, 2018Assignee: Invensas CorporationInventors: Zhuowen Sun, Kyong-Mo Bang, Belgacem Haba, Wael Zohni
-
Patent number: 9911717Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.Type: GrantFiled: March 16, 2015Date of Patent: March 6, 2018Assignee: Invensas CorporationInventors: Belgacem Haba, Kyong-Mo Bang
-
Patent number: 9847238Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.Type: GrantFiled: February 27, 2017Date of Patent: December 19, 2017Assignee: Invensas CorporationInventors: Xuan Li, Rajesh Katkar, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara, Tu Tam Vu, Kyong-Mo Bang, Akash Agrawal
-
Publication number: 20170323667Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.Type: ApplicationFiled: May 15, 2017Publication date: November 9, 2017Applicant: Invensas CorporationInventors: Zhuowen Sun, Kyong-Mo Bang, Belgacem Haba, Wael Zohni
-
Publication number: 20170294410Abstract: A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.Type: ApplicationFiled: April 11, 2016Publication date: October 12, 2017Inventors: Belgacem Haba, Kyong-Mo Bang
-
Publication number: 20170170031Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Applicant: Invensas CorporationInventors: Xuan Li, Rajesh Katkar, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara, Tu Tam Vu, Kyong-Mo Bang, Akash Agrawal
-
Patent number: 9679613Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.Type: GrantFiled: May 6, 2016Date of Patent: June 13, 2017Assignee: Invensas CorporationInventors: Zhuowen Sun, Kyong-Mo Bang, Belgacem Haba, Wael Zohni
-
Publication number: 20170133081Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.Type: ApplicationFiled: October 28, 2016Publication date: May 11, 2017Inventors: Zhuowen Sun, Yong Chen, Kyong-Mo Bang
-
Patent number: 9646946Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.Type: GrantFiled: October 7, 2015Date of Patent: May 9, 2017Assignee: Invensas CorporationInventors: Xuan Li, Rajesh Katkar, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara, Tu Tam Vu, Kyong-Mo Bang, Akash Agrawal
-
Publication number: 20170103957Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.Type: ApplicationFiled: October 7, 2015Publication date: April 13, 2017Applicant: Invensas CorporationInventors: Xuan Li, Rajesh Katkar, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara, Tu Tam Vu, Kyong-Mo Bang, Akash Agrawal
-
Publication number: 20170069591Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Applicant: Invensas CorporationInventors: Rajesh Katkar, Tu Tam Vu, Bongsub Lee, Kyong-Mo Bang, Xuan Li, Long Huynh, Gabriel Z. Guevara, Akash Agrawal, Willmar Subido, Laura Wills Mirkarimi
-
Patent number: 9543277Abstract: A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which may have additional traces thereon, with contacts at a fan-out area of a dielectric element adjacent an edge surface of the chip. The bond wires mechanically decouple the microelectronic element from the fan-out area, which can make the electrical interconnections less prone to reliability issues due to effects of differential thermal expansion, such as caused by temperature excursions during initial package fabrication, bonding operations or thermal cycling. In addition, mechanical decoupling provided by the bond wires may also remedy other mechanical issues such as shock and possible delamination of package elements.Type: GrantFiled: August 20, 2015Date of Patent: January 10, 2017Assignee: Invensas CorporationInventors: Bongsub Lee, Tu Tam Vu, Rajesh Katkar, Laura Wills Mirkarimi, Akash Agrawal, Kyong-Mo Bang, Gabriel Z. Guevara, Xuan Li, Long Huynh
-
Patent number: 9502372Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.Type: GrantFiled: April 30, 2015Date of Patent: November 22, 2016Assignee: Invensas CorporationInventors: Rajesh Katkar, Tu Tam Vu, Bongsub Lee, Kyong-Mo Bang, Xuan Li, Long Huynh, Gabriel Z. Guevara, Akash Agrawal, Willmar Subido, Laura Wills Mirkarimi
-
Patent number: 9496242Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.Type: GrantFiled: March 16, 2015Date of Patent: November 15, 2016Assignee: Invensas CorporationInventors: Belgacem Haba, Kyong-Mo Bang