Patents by Inventor Kyong Sik YEOM

Kyong Sik YEOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862632
    Abstract: A semiconductor device includes a first gate electrode structure having a first gate insulating layer on a substrate and a first gate electrode on the first gate insulating layer. A first spacer structure includes a first spacer and a second spacer on side walls of the first gate electrode structure. The first spacer is disposed between the second spacer and the first gate electrode. A source/drain region is disposed on opposite sides of the first gate electrode structure. The first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, and the first spacer is disposed on the side wall of the upper pan of the first gate electrode and is not disposed on the side wall of the lower part of the first gate electrode.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Kyong-Sik Yeom, Young Cheon Jeong
  • Publication number: 20220059529
    Abstract: A semiconductor device includes a first gate electrode structure having a first gate insulating layer on a substrate and a first gate electrode on the first gate insulating layer. A first spacer structure includes a first spacer and a second spacer on side walls of the first gate electrode structure. The first spacer is disposed between the second spacer and the first gate electrode. A source/drain region is disposed on opposite sides of the first gate electrode structure. The first gate electrode includes a lower part of the first gate electrode, an upper part of the first gate electrode disposed on the lower part of the first gate electrode, and the first spacer is disposed on the side wall of the upper pan of the first gate electrode and is not disposed on the side wall of the lower part of the first gate electrode.
    Type: Application
    Filed: April 21, 2021
    Publication date: February 24, 2022
    Inventors: KYONG-SIK YEOM, YOUNG CHEON JEONG
  • Patent number: 9728544
    Abstract: A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tea Kwang Yu, Yong Tae Kim, Jae Hyun Park, Kyong Sik Yeom
  • Publication number: 20160148944
    Abstract: A method of manufacturing a semiconductor device may include forming split gate structures including a floating gate electrode layer and a control gate electrode layer in a cell region of a substrate including the cell region and a logic region adjacent to the cell region. The method may include sequentially forming a first gate insulating film and a metal gate film in the logic region and the cell region, removing the metal gate film from at least a portion of the cell region and the logic region, forming a second gate insulating film on the first gate insulating film from which the metal gate film has been removed, forming a gate electrode film on the logic region and the cell region, and forming a plurality of memory cell elements disposed in the cell region and a plurality of circuit elements disposed in the logic region.
    Type: Application
    Filed: October 21, 2015
    Publication date: May 26, 2016
    Inventors: Tea Kwang YU, Yong Tae KIM, Jae Hyun PARK, Kyong Sik YEOM