Patents by Inventor Kyong-Jin HWANG

Kyong-Jin HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031457
    Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 23, 2025
    Inventors: Sagar Premnath Karalkar, . Ajay, Souvick Mitra, Kyong Jin Hwang
  • Publication number: 20240429227
    Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises adjacent first and second gates over a semiconductor substrate, a source adjacent to the first gate, and a drain adjacent to the second gate. The source includes a first well in the semiconductor substrate, a second well in the semiconductor substrate, and a doped region. The first well and the doped region have a first conductivity type, and the second well has a second conductivity type opposite from the first conductivity type. The doped region has a first portion that overlaps with the first well, and the doped region has a second portion that overlaps with the second well.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Sagar Premnath Karalkar, Vishal Ganesan, Kyong Jin Hwang, Souvick Mitra
  • Publication number: 20240363619
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a semiconductor material of a first dopant type; a first well having a second dopant type in the semiconductor material; a floating well in the first well, the second well having the first dopant type; and a diffusion region of the second dopant type adjacent to the floating well and in electrical contact to the first well.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 31, 2024
    Inventors: Kyong Jin HWANG, Jie ZENG, Ajay AJAY
  • Publication number: 20240363740
    Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate having an upper substrate surface, an active well region, a first terminal well region, and a second terminal well region. The active well region is in the substrate, and the first terminal well region and the second terminal well region are in the active well region. The second terminal well region is spaced apart from the first terminal well region. The first terminal well region and the second terminal well region each includes a first doped region, a first contact region having at least a portion in the first doped region, and a second contact region spaced apart from the first doped region.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: SAGAR PREMNATH KARALKAR, KYONG JIN HWANG, JOSEPH JAMES JERRY
  • Patent number: 12057442
    Abstract: The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: August 6, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Kyong Jin Hwang, Hyun Kwang Jeong
  • Publication number: 20240243118
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic devices and methods of manufacture. The structure includes: a device having a collector, an emitter, and a base; an isolation structure extending between the base and the collector; a high resistivity film over the isolation structure; and a silicide blocking layer partially covering the high resistivity film, the isolation structure and the collector.
    Type: Application
    Filed: January 13, 2023
    Publication date: July 18, 2024
    Inventors: Jie ZENG, Kyong Jin HWANG, Namchil MUN, Shiang Yang ONG
  • Patent number: 11990466
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: May 21, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kyong Jin Hwang, Robert J. Gauthier, Jr., Jie Zeng
  • Patent number: 11978733
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 7, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kyong Jin Hwang, Milova Paul, Sagar P. Karalkar, Robert J. Gauthier, Jr.
  • Patent number: 11942472
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a vertical silicon-controlled rectifier (SCR) connecting to an anode, and includes a buried layer of a first dopant type in electrical contact with an underlying buried layer a second dopant type split with an isolation region of the first dopant type within a substrate.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 26, 2024
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kyong Jin Hwang, Milova Paul, Sagar Premnath Karalkar, Robert J. Gauthier, Jr.
  • Patent number: 11824125
    Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 21, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Sagar Premnath Karalkar, James Jerry Joseph, Jie Zeng, Milova Paul, Kyong Jin Hwang
  • Patent number: 11749672
    Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 5, 2023
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Prantik Mahajan, Aloysius Priartanto Herlambang, Kyong Jin Hwang, Robert John Gauthier, Jr.
  • Publication number: 20230130632
    Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, an active region, a first terminal region, and a second terminal region. The substrate includes dopants having a first dopant conductivity. The active region is arranged over the substrate and has an upper surface. The first terminal region and the second terminal region are arranged in the active region laterally spaced apart from each other. The first terminal region and the second terminal region each include a well region having dopants of the first dopant conductivity and a first doped region arranged in the well region. The first doped region includes dopants having a second dopant conductivity.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Inventors: SAGAR PREMNATH KARALKAR, JAMES JERRY JOSEPH, JIE ZENG, MILOVA PAUL, KYONG JIN HWANG
  • Publication number: 20230121127
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventors: Kyong Jin HWANG, Robert J. GAUTHIER, JR., Jie ZENG
  • Publication number: 20230085420
    Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Prantik MAHAJAN, Aloysius Priartanto HERLAMBANG, Kyong Jin HWANG, Robert John GAUTHIER, JR.
  • Publication number: 20230078157
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Kyong Jin HWANG, Milova PAUL, Sagar Premnath Karalkar, Robert J. Gauthier, JR.
  • Publication number: 20230039286
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure comprising a vertical silicon controlled rectifier (SCR) connecting to an anode, and comprising a buried layer of a first dopant type in electrical contact with an underlying continuous layer of a second dopant type within a substrate.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Inventors: Kyong Jin HWANG, Milova PAUL, Sagar P. Karalkar, Robert J. Gauthier, Jr.
  • Patent number: 11476244
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: October 18, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Prantik Mahajan, Elaine Xiao Mei Low, Kyong Jin Hwang
  • Patent number: 11398565
    Abstract: A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 26, 2022
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Prantik Mahajan, Raunak Kumar, Kyong Jin Hwang, Robert JR Gauthier, Jr.
  • Publication number: 20220181474
    Abstract: A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: PRANTIK MAHAJAN, RAUNAK KUMAR, KYONG JIN HWANG, ROBERT JR GAUTHIER JR
  • Publication number: 20220059525
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. First and second source/drain regions are formed in a substrate, a gate electrode is formed over the substrate, an interconnect structure over the substrate, and a doped region is arranged in the substrate beneath the first source/drain region. The gate electrode is laterally positioned between the first and second source/drain regions, and the interconnect structure includes a contact connected to the first source/drain region. The doped region has a side edge that is laterally spaced from the contact by a distance.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 24, 2022
    Inventors: Prantik Mahajan, Elaine Xiao Mei Low, Kyong Jin Hwang