Abstract: The ?-ketoimine ligand is represented by the following formula 1: wherein R1 and R2 are each independently a C1-C5 alkyl group. A metal complex compound includes the ?-ketoimine ligand. A method of forming the ?-ketoimine ligand and a method of forming a thin film using the metal complex compound including ?-ketoimine ligand are provided.

Abstract: The ?-ketoimine ligand is represented by the following formula 1: wherein R1 and R2 are each independently a C1-C5 alkyl group. A metal complex compound includes the ?-ketoimine ligand. A method of forming the ?-ketoimine ligand and a method of forming a thin film using the metal complex compound including ?-ketoimine ligand are provided.

Abstract: A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

Abstract: The ?-ketoimine ligand is represented by the following formula 1: wherein R1 and R2 are each independently a C1-C5 alkyl group. A metal complex compound includes the ?-ketoimine ligand. A method of forming the ?-ketoimine ligand and a method of forming a thin film using the metal complex compound including ?-ketoimine ligand are provided.

Abstract: The ?-ketoimine ligand is represented by the following formula 1: wherein R1 and R2 are each independently a C1-C5 alkyl group. A metal complex compound includes the ?-ketoimine ligand. A method of forming the ?-ketoimine ligand and a method of forming a thin film using the metal complex compound including ?-ketoimine ligand are provided.

Abstract: The ?-ketoimine ligand is represented by the following formula 1: wherein R1 and R2 are each independently a C1-C5 alkyl group. A metal complex compound includes the ?-ketoimine ligand. A method of forming the ?-ketoimine ligand and a method of forming a thin film using the metal complex compound including ?-ketoimine ligand are provided.

Abstract: Disclosed are an organometallic precursor that may be used in manufacturing a semiconductor device, a thin film having the same, a metal wiring including the thin film, a method of forming a thin film and a method of manufacturing a metal wiring. An organometallic precursor including a central metal, a borohydride ligand and an amine ligand for reducing a polarity of the organometallic precursor may be provided onto a substrate, and may be thermally decomposed to form a thin film on the substrate. The organometallic precursor having a reduced polarity may be provided to a chamber with a constant flow rate, and thus stability and/or efficiency of a semiconductor manufacturing process may be improved.

Abstract: A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: Provided herein are methods of forming a metal oxide layer that include providing an organometallic compound and an oxidizing agent to the substrate to form the metal oxide layer on the substrate. The organometallic compound may have the general formula of M(NR1R2)3R3, wherein M is a metal; R1 and R2 are each independently hydrogen or alkyl; and R3 is selected from the group consisting of alkyl, cycloalkyl, heterocycloalkyl, aryl and heteroaryl.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: A metal organic precursor represented by a formula of R1-CpML is provided onto a substrate having a conductive pattern including silicon. Here, R1 is an alkyl group substituent of Cp, R1 including methyl, ethyl, propyl, pentamethyl, pentaethyl, diethyl, dimethyl or dipropyl, Cp is cyclopentadienyl, M includes nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt) zirconium (Zr) or ruthenium (Ru), and L is at least one ligand, the at least one ligand including a carbonyl. A deposition process is performed using the metal organic precursor to form a preliminary metal silicide layer and a metal layer on the substrate. The preliminary metal silicidation layer is formed on the conductive pattern. The preliminary metal silicide layer is transformed into a metal silicide layer.

Abstract: Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.

Abstract: An organic aluminum precursor includes aluminum as a central metal, and borohydride and trimethylamine as ligands. In a method of forming an aluminum layer or wire, the organic aluminum presursor is introduced onto a substrate, and then thermally decomposed. The aluminum decomposed from the organic aluminum precursor is deposited on the substrate.

Abstract: Disclosed are an organometallic precursor that may be used in manufacturing a semiconductor device, a thin film having the same, a metal wiring including the thin film, a method of forming a thin film and a method of manufacturing a metal wiring. An organometallic precursor including a central metal, a borohydride ligand and an amine ligand for reducing a polarity of the organometallic precursor may be provided onto a substrate, and may be thermally decomposed to form a thin film on the substrate. The organometallic precursor having a reduced polarity may be provided to a chamber with a constant flow rate, and thus stability and/or efficiency of a semiconductor manufacturing process may be improved.

Abstract: In a method of manufacturing a metal wiring, an organic aluminum precursor that includes aluminum as a central metal is applied to a substrate. The organic aluminum precursor applied to the substrate is thermally decomposed to form aluminum. The aluminum is deposited on the substrate to form an aluminum wiring having a low resistance. The organic aluminum precursor includes a chemical structure in accordance with one of the chemical formulae: wherein R1, R2, R3, R4 and R5 are independently H or a C1-C5 alkyl functional group, n is an integer of 1 to 5, x is 1 or 2, and y is 0 or 1, or wherein R1, R2, R3, R4 R5, R6, R7 and R8 are independently H or a C1-C5 alkyl functional group, and Y is boron.

Abstract: In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.