Patents by Inventor Kyoshi Nishimura

Kyoshi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120224372
    Abstract: The light source unit is provided with a substrate and a decorative cover having thermal conductivity. The substrate includes a circuit pattern area, in which a plurality of LED chips are disposed, at the middle part thereof, has thermal conductivity, and transmits heat from the circuit pattern area to an area in the outer circumferential direction thereof. The decorative cover encloses the substrate, is electrically insulated from the circuit pattern area, and is thermally coupled to the surface side of the substrate at the periphery of the circuit pattern area by being face-contacted thereto. Heat of the substrate can be radiated by the decorative cover while securing an electric insulation property with respect to the circuit pattern area.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION
    Inventors: Kozo Ogawa, Kyoshi Nishimura, Nobuhiko Betsuda, Hiroki Tamai, Akiko Saito
  • Patent number: 6240013
    Abstract: A data holding apparatus that is capable of a high speed response and that holds data even when the power source is off. Each memory cell of the data holding apparatus includes first and second transistors, where at least the first transistor is a ferroelectric transistor having a floating gate over the gate insulating film, and a ferroelectric layer between the gate insulating layer and the control gate. The control gate of the first transistor is connected to the drain of the second transistor and the control gate of the second transistor is connected to the drain of the first transistor to provide a positive feedback to each other, and the memory cell holds data defined by the ON or OFF states of the first and second transistors. The memory cell further includes data lines carrying data signals to be written into or read from the memory cell.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: May 29, 2001
    Assignee: Rohm Co., Ltd.
    Inventor: Kyoshi Nishimura