Patents by Inventor KYOSUKE KOBINATA
KYOSUKE KOBINATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12451365Abstract: A package device manufacturing method is provided. In the manufacturing method, device chips are disposed on first regions of a workpiece, and a mold resin is supplied to second regions higher than the first regions and the first regions. Further, the mold resin is processed and thinned to a thickness with which the second regions of the workpiece are not exposed, and the mold resin is polished to expose the second regions of the workpiece and form, in the workpiece, a flat surface including the mold resin and the second regions, the mold resin being disposed on the first regions. Moreover, the workpiece is divided to manufacture the individual package devices.Type: GrantFiled: November 15, 2022Date of Patent: October 21, 2025Assignee: DISCO CORPORATIONInventor: Kyosuke Kobinata
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Patent number: 12383982Abstract: A laminated device wafer forming method includes a laminating step of laminating a first device wafer and a second device wafer to each other, the laminating step including a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside rectangular regions corresponding to devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices, and adjusting relative positions of the first device wafer and the second device wafer by using the first predetermined line and the second predetermined line.Type: GrantFiled: July 7, 2022Date of Patent: August 12, 2025Assignee: DISCO CORPORATIONInventors: Zhiwen Chen, Kyosuke Kobinata, Shunsuke Teranishi, Akihito Kawai
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Patent number: 12322655Abstract: A method of manufacturing a layered device chip assembly includes forming first grooves in a first wafer, fixing the first wafer to a support body, grinding the first wafer to expose the first grooves, forming a first resin layer in the first grooves, simultaneously polishing the first wafer and the first resin layer to expose the first resin layer, forming second grooves in the second wafer, the second grooves having a width on the face side larger than a width of the first grooves and a width at groove bottoms that is smaller than the width on the face side of the second wafer, affixing the second wafer to the first wafer, grinding the second wafer to expose the second grooves on the reverse side thereof, forming a second resin layer in the second grooves, and dividing the first wafer and the second wafer into a plurality of assemblies.Type: GrantFiled: September 22, 2022Date of Patent: June 3, 2025Assignee: DISCO CORPORATIONInventors: Shunsuke Teranishi, Zhiwen Chen, Kyosuke Kobinata, Akihito Kawai
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Patent number: 11646328Abstract: An imaging device including a semiconductor substrate; a first pixel including a first photoelectric converter configured to convert incident light into charge, and a first diffusion region in the semiconductor substrate, configured to electrically connected to the first photoelectric converter and a second pixel including a second photoelectric converter, configured to convert incident light into charge, and a second diffusion region in the semiconductor substrate, configured to electrically connected to the second photoelectric converter, wherein an area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, both the first diffusion region and the second diffusion region overlap with the first photoelectric converter in the plan view, and neither the first diffusion region nor the second diffusion region overlaps with the second photoelectric converter in the plan view.Type: GrantFiled: September 30, 2020Date of Patent: May 9, 2023Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kyosuke Kobinata, Sanshiro Shishido, Yoshihiro Sato
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Publication number: 20230096486Abstract: A method of manufacturing a layered device chip assembly includes forming first grooves in a first wafer, fixing the first wafer to a support body, grinding the first wafer to expose the first grooves, forming a first resin layer in the first grooves, simultaneously polishing the first wafer and the first resin layer to expose the first resin layer, forming second grooves in the second wafer, the second grooves having a width on the face side larger than a width of the first grooves and a width at groove bottoms that is smaller than the width on the face side of the second wafer, affixing the second wafer to the first wafer, grinding the second wafer to expose the second grooves on the reverse side thereof, forming a second resin layer in the second grooves, and dividing the first wafer and the second wafer into a plurality of assemblies.Type: ApplicationFiled: September 22, 2022Publication date: March 30, 2023Inventors: Shunsuke TERANISHI, Zhiwen CHEN, Kyosuke KOBINATA, Akihito KAWAI
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Publication number: 20230020620Abstract: A laminated device wafer forming method includes a laminating step of laminating a first device wafer and a second device wafer to each other, the laminating step including a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside rectangular regions corresponding to devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices, and adjusting relative positions of the first device wafer and the second device wafer by using the first predetermined line and the second predetermined line.Type: ApplicationFiled: July 7, 2022Publication date: January 19, 2023Inventors: Zhiwen CHEN, Kyosuke KOBINATA, Shunsuke TERANISHI, Akihito KAWAI
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Publication number: 20210013252Abstract: An imaging device including a semiconductor substrate; a first pixel including a first photoelectric converter configured to convert incident light into charge, and a first diffusion region in the semiconductor substrate, configured to electrically connected to the first photoelectric converter and a second pixel including a second photoelectric converter, configured to convert incident light into charge, and a second diffusion region in the semiconductor substrate, configured to electrically connected to the second photoelectric converter, wherein an area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, both the first diffusion region and the second diffusion region overlap with the first photoelectric converter in the plan view, and neither the first diffusion region nor the second diffusion region overlaps with the second photoelectric converter in the plan view.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Kyosuke KOBINATA, Sanshiro SHISHIDO, Yoshihiro SATO
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Patent number: 10825846Abstract: An imaging device includes: a semiconductor substrate; a first pixel including: a first photoelectric converter above the semiconductor substrate, including first and second electrodes and a first photoelectric conversion layer between the first and second electrodes, configured to convert incident light into first charge; and a first charge accumulation region in the semiconductor substrate, electrically connected to the second electrode; and a second pixel including a second photoelectric converter above the semiconductor substrate, including third and fourth electrodes and a second photoelectric conversion layer between the third and fourth electrodes, configured to convert incident light into second charge; and a second charge accumulation region in the semiconductor substrate, electrically connected to the fourth electrode.Type: GrantFiled: July 12, 2018Date of Patent: November 3, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kyosuke Kobinata, Sanshiro Shishido, Yoshihiro Sato
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Publication number: 20190035832Abstract: An imaging device includes: a semiconductor substrate; a first pixel including: a first photoelectric converter above the semiconductor substrate, including first and second electrodes and a first photoelectric conversion layer between the first and second electrodes, configured to convert incident light into first charge; and a first charge accumulation region in the semiconductor substrate, electrically connected to the second electrode; and a second pixel including a second photoelectric converter above the semiconductor substrate, including third and fourth electrodes and a second photoelectric conversion layer between the third and fourth electrodes, configured to convert incident light into second charge; and a second charge accumulation region in the semiconductor substrate, electrically connected to the fourth electrode.Type: ApplicationFiled: July 12, 2018Publication date: January 31, 2019Inventors: KYOSUKE KOBINATA, SANSHIRO SHISHIDO, YOSHIHIRO SATO