Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device includes: repeating multiple times of a process of etching away one pair of first and second insulating layers of a stacked body exposed from a second mask layer, among a plurality of first and second insulating layers, with retracting the second mask layer in a first direction toward a first side by slimming; removing the second mask layer undergone multiple times of the slimming; removing a first stopper layer exposed on the first side; and repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from a first mask layer, among the plurality of first and second insulating layers, with retracting the first mask layer in the first direction by slimming.

Abstract: A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one; and a plurality of first plate-like portions that penetrate the stacked body in a stacking direction thereof and cross the stacked body in a first direction intersecting the stacking direction, the plurality of first plate-like portions being arranged along the first direction with a gap therebetween.

Abstract: According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.

Abstract: According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.