Abstract: A memory includes a stack of electrode films and first insulation films alternately stacked in a first direction. A first column body includes a semiconductor layer penetrating through the stack in the first direction and forms a memory cell. First pillar portions penetrate through the stack in the first direction and are an insulation material. Second pillar portions penetrate through the stack in the first direction, are a conductive material, and correspond to and are electrically connected to the electrode films, respectively. Assuming a connected electrode film connected to one of the second pillar portions as a boundary, a width of one of the second pillar portions in a plane perpendicular to the first direction is different between a pillar upper portion located above the connected electrode film in the first direction and a pillar lower portion located below the connected electrode film in the first direction.

Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device includes: repeating multiple times of a process of etching away one pair of first and second insulating layers of a stacked body exposed from a second mask layer, among a plurality of first and second insulating layers, with retracting the second mask layer in a first direction toward a first side by slimming; removing the second mask layer undergone multiple times of the slimming; removing a first stopper layer exposed on the first side; and repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from a first mask layer, among the plurality of first and second insulating layers, with retracting the first mask layer in the first direction by slimming.

Abstract: A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one; and a plurality of first plate-like portions that penetrate the stacked body in a stacking direction thereof and cross the stacked body in a first direction intersecting the stacking direction, the plurality of first plate-like portions being arranged along the first direction with a gap therebetween.

Abstract: A semiconductor storage device includes a stacked body having a plurality of conductive layers and a plurality of first insulating layers that are alternately stacked, and a staircase portion in which the plurality of conductive layers have been processed into a staircase shape, a contact disposed in the staircase portion and connected to a first conductive layer, which is one of the plurality of conductive layers, and a first pillar that extends in a stacking direction of the stacked body in a portion of the stacked body different from the staircase portion and forms memory cells at each intersection of the first pillar and at least a part of the plurality of conductive layers. The contact penetrates a second conductive layer, which is not one of the plurality of conductive layers and disposed above the first conductive layer, and reaches the first conductive layer to be in contact therewith.

Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device includes: repeating multiple times of a process of etching away one pair of first and second insulating layers of a stacked body exposed from a second mask layer, among a plurality of first and second insulating layers, with retracting the second mask layer in a first direction toward a first side by slimming; removing the second mask layer undergone multiple times of the slimming; removing a first stopper layer exposed on the first side; and repeating multiple times of a process of etching away one pair of first and second insulating layers of the stacked body exposed from a first mask layer, among the plurality of first and second insulating layers, with retracting the first mask layer in the first direction by slimming.

Abstract: A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one; and a plurality of first plate-like portions that penetrate the stacked body in a stacking direction thereof and cross the stacked body in a first direction intersecting the stacking direction, the plurality of first plate-like portions being arranged along the first direction with a gap therebetween.

Abstract: According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.

Abstract: According to one embodiment, a semiconductor memory device includes: a stack body having a step structure body with a plurality of wire line layers and a plurality of interlayer insulating layers alternately stacked being set as one step on a substrate; and memory cells arranged three-dimensionally in the stack body, in which the step structure body includes: a plurality of terrace portions configured with the interlayer insulating layers, the plurality of terrace portions having different heights; a plurality of step portions connecting the respective terrace portions in a height direction; insulating layers covering the step portions; and a lead wire line leading out a lowermost wire line layer of a first step onto the terrace portion of a second step being a lower step of the first step.