Abstract: A design support apparatus according to an aspect of the present invention includes: a terminal position setting unit that obtains, from a floor plan result generated from circuit design information, positional information on first and second connection terminals of a connection target circuit area to be connected to an inductor to be generated, and sets third and fourth connection terminals at respective positions where the first and third connection terminals and the second and fourth connection terminals can be respectively connected by a shortest wiring, the third and fourth connection terminals connecting the inductor to another circuit; and a pattern generation unit that generates a wiring pattern of the inductor based on the positions of the third and fourth connection terminals, and generates layout information on the inductor based on the wiring pattern.

Abstract: Circuit diagram data having repeated patterns is divided by the process of group dividing into main patterns and replicated patterns, relations of each of the patterns are held as group composition information, replicated pattern layout data corresponding to replicated patterns is made by copying the main pattern layout data corresponding to the main patterns made by a net driven layout editor, and the process of offset arrangement which involves shifting the coordinates of the replicated pattern layout data is performed, thereby making it possible to arrange the replicated pattern layout data on the same hierarchical level as the main pattern layout data and to make layout data with the flat circuit diagram data kept as it is.

Abstract: A mask pattern data creation method which automatically reflects changes made to layout cell data upon correcting the layout cell data hierarchically lower than mask pattern data, and eliminates the need for a user to manually perform deletion processing or layout processing in order to prevent human errors that may be introduced into layout data on the layout cell data to be laid out in the mask pattern data. The method places the layout cell data hierarchically below dummy cell data based on the layout data of entered layout cell data and then places the dummy cell data hierarchically below the mask pattern data, adds the layout data on the layout cell data to the dummy cell data, and creates graphic data corresponding to an angle specified in the layout data by expanding the layout cell data below the dummy cell data. When correcting the layout cell data, the system reads the layout data added to the dummy cell data and deletes the graphic data from the dummy cell data.

Abstract: A design rule check is to inspect whether mask pattern data of a semiconductor integrated circuit is correctly designed in accordance with a design standard or not. A design rule check method of the present invention is characterized in that design rule check errors occurring in the design rule check between a first error and a second error output in accordance with whether the design rule check errors overlap or not.

Abstract: A method for performing simulation of a semiconductor integrated circuit is disclosed in which a circuit simulation result taking into consideration can be obtained relative variation. In the method, possible maximum and minimum values of an element parameter, i.e., element parameters of a worst case taking into consideration the relative variation is determined from prescribed absolute and relative variation ranges to form a variation model. Based on the variation model, worst-case simulation is carried out taking into account the relative variation.